| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | UnreachableBlockElim.cpp | 167 Register InputReg = Input.getReg(); in runOnMachineFunction() local
172 if (InputReg != OutputReg) { in runOnMachineFunction()
176 MRI.constrainRegClass(InputReg, MRI.getRegClass(OutputReg)) && in runOnMachineFunction()
178 MRI.replaceRegWith(OutputReg, InputReg); in runOnMachineFunction()
187 .addReg(InputReg, getRegState(Input), InputSub); in runOnMachineFunction()
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| H A D | TargetInstrInfo.cpp | 1295 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregInputs()
1300 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1312 InputReg.Reg = MOReg.getReg(); in getExtractSubregInputs()
1313 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
1314 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 814 LI->getImplicitArgPtr(InputReg, MRI, MIRBuilder); in passSpecialInputs()
819 MIRBuilder.buildConstant(InputReg, Id.value()); in passSpecialInputs()
821 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
826 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
874 Register InputReg; in passSpecialInputs() local
893 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Y).getReg(0) : Y; in passSpecialInputs()
903 InputReg = InputReg ? MIRBuilder.buildOr(S32, InputReg, Z).getReg(0) : Z; in passSpecialInputs()
906 if (!InputReg && in passSpecialInputs()
908 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
914 MIRBuilder.buildUndef(InputReg); in passSpecialInputs()
[all …]
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| H A D | SILowerControlFlow.cpp | 726 Register InputReg = MI.getOperand(0).getReg(); in lowerInitExec() local
728 if (InputReg.isVirtual()) { in lowerInitExec()
729 MachineInstr *DefInstr = MRI->getVRegDef(InputReg); in lowerInitExec()
752 .addReg(InputReg) in lowerInitExec()
755 LV->recomputeForSingleDefVirtReg(InputReg); in lowerInitExec()
785 LIS->removeInterval(InputReg); in lowerInitExec()
786 LIS->createAndComputeVirtRegInterval(InputReg); in lowerInitExec()
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| H A D | SIFixSGPRCopies.cpp | 849 Register InputReg = MI.getOperand(i).getReg(); in processPHINode() local
850 MachineInstr *Def = MRI->getVRegDef(InputReg); in processPHINode()
851 if (TRI->isVectorRegister(*MRI, InputReg)) { in processPHINode()
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| H A D | SIISelLowering.cpp | 2818 SDValue InputReg; in passSpecialInputs() local
2825 InputReg = getImplicitArgPtr(DAG, DL); in passSpecialInputs()
2831 InputReg = DAG.getUNDEF(ArgVT); in passSpecialInputs()
2836 InputReg = DAG.getUNDEF(ArgVT); in passSpecialInputs()
2876 SDValue InputReg; in passSpecialInputs() local
2889 InputReg = DAG.getConstant(0, DL, MVT::i32); in passSpecialInputs()
2898 InputReg = InputReg.getNode() ? in passSpecialInputs()
2907 InputReg = InputReg.getNode() ? in passSpecialInputs()
2917 InputReg = DAG.getUNDEF(MVT::i32); in passSpecialInputs()
2930 if (InputReg) in passSpecialInputs()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 2527 Register InputReg = getRegForValue(I->getOperand(0)); in X86SelectTrunc() local
2528 if (!InputReg) in X86SelectTrunc()
2534 updateValueMap(I, InputReg); in X86SelectTrunc()
2598 Register InputReg = getRegForValue(Op); in fastLowerIntrinsicCall() local
2599 if (InputReg == 0) in fastLowerIntrinsicCall()
2624 InputReg = fastEmitInst_ri(Opc, RC, InputReg, 4); in fastLowerIntrinsicCall()
2631 .addReg(InputReg, RegState::Kill); in fastLowerIntrinsicCall()
2639 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg); in fastLowerIntrinsicCall()
2643 InputReg); in fastLowerIntrinsicCall()
2647 InputReg = fastEmitInst_r(Opc, RC, InputReg); in fastLowerIntrinsicCall()
[all …]
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 551 RegSubRegPairAndIdx &InputReg) const;
1262 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs() argument
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1394 Register InputReg = getRegForValue(I->getOperand(0)); in selectCast() local
1395 if (!InputReg) in selectCast()
1400 Opcode, InputReg); in selectCast()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 75 RegSubRegPairAndIdx &InputReg) const override;
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| H A D | ARMBaseInstrInfo.cpp | 5460 RegSubRegPairAndIdx &InputReg) const { in getExtractSubregLikeInputs()
5473 InputReg.Reg = MOReg.getReg(); in getExtractSubregLikeInputs()
5474 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregLikeInputs()
5475 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1; in getExtractSubregLikeInputs()
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