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Searched refs:Inp (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp1575 if (!BT.has(Inp.Reg)) in findMatch()
1578 auto *FRC = HBS::getFinalVRegClass(Inp, MRI); in findMatch()
1580 if (!HBS::getSubregMask(Inp, B, W, MRI)) in findMatch()
1591 if (!HBS::isTransparentCopy(R, Inp, MRI)) in findMatch()
1614 if (HBS::isTransparentCopy(Out, Inp, MRI)) in findMatch()
2948 BitTracker::RegisterRef Inp, Out; member
3111 .addReg(G.Inp.Reg) in moveGroup()
3113 RegMap.insert(std::make_pair(G.Inp.Reg, PhiR)); in moveGroup()
3281 G.Inp.Reg = Inputs.find_first(); in processLoop()
3289 << printReg(G.Inp.Reg, HRI, G.Inp.Sub) in processLoop()
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H A DHexagonISelDAGToDAGHVX.cpp670 ResultStack(SDNode *Inp) in ResultStack()
671 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack()
1126 OpRef Inp[2] = {Va, Vb}; in packs() local
1199 return Inp[SrcOp]; in packs()
1231 Va = Inp[Seg0 / 2]; in packs()
1234 Results.push(Hexagon::V6_vror, Ty, {Inp[Seg0 / 2], HL}); in packs()
1356 OpRef Inp[2] = { Va, Vb }; in packp() local
1364 OpRef Op = Inp[S / 2]; in packp()
H A DHexagonISelDAGToDAG.cpp921 SDValue Inp = Op, Res; in SelectInlineAsmMemoryOperand() local
929 if (SelectAddrFI(Inp, Res)) in SelectInlineAsmMemoryOperand()
932 OutOps.push_back(Inp); in SelectInlineAsmMemoryOperand()
/llvm-project-15.0.7/compiler-rt/lib/fuzzer/
H A DFuzzerDriver.cpp893 for (auto &Inp : *Inputs) { in FuzzerDriver()
894 Printf("Loading corpus dir: %s\n", Inp.c_str()); in FuzzerDriver()
895 ReadDirToVectorOfUnits(Inp.c_str(), &InitialCorpus, nullptr, in FuzzerDriver()
/llvm-project-15.0.7/clang-tools-extra/clangd/unittests/
H A DTUSchedulerTests.cpp1352 S.runWithAST(Path, Path, [](llvm::Expected<InputsAndAST> Inp) { in TEST_F() argument
1353 EXPECT_TRUE(bool(Inp)); in TEST_F()
1361 [](llvm::Expected<InputsAndPreamble> Inp) { EXPECT_TRUE(bool(Inp)); }); in TEST_F() argument
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13519 SDValue Inp = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, in PerformADDVecReduce() local
13521 NA = DAG.getNode(ISD::ADD, dl, MVT::i64, Inp, NA); in PerformADDVecReduce()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp47773 SDValue Inp = (i == 0) ? Node->getOperand(1) : Node->getOperand(0); in combineAndLoadToBZHI() local
47788 return DAG.getNode(ISD::AND, dl, VT, Inp, LShr); in combineAndLoadToBZHI()