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/llvm-project-15.0.7/clang-tools-extra/clangd/refactor/
H A DRename.cpp874 assert(!Indexed.empty()); in adjustRenameRanges()
875 assert(std::is_sorted(Indexed.begin(), Indexed.end())); in adjustRenameRanges()
879 return getMappedRanges(Indexed, Lexed); in adjustRenameRanges()
885 assert(!Indexed.empty()); in getMappedRanges()
886 assert(std::is_sorted(Indexed.begin(), Indexed.end())); in getMappedRanges()
889 if (Indexed.size() > Lexed.size()) { in getMappedRanges()
897 if (std::includes(Indexed.begin(), Indexed.end(), Lexed.begin(), Lexed.end())) in getMappedRanges()
898 return Indexed.vec(); in getMappedRanges()
952 assert(Indexed.size() == MappedIndex.size()); in renameRangeAdjustmentCost()
953 assert(std::is_sorted(Indexed.begin(), Indexed.end())); in renameRangeAdjustmentCost()
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H A DRename.h84 std::vector<Range> Indexed, const LangOptions &LangOpts);
92 llvm::Optional<std::vector<Range>> getMappedRanges(ArrayRef<Range> Indexed,
100 size_t renameRangeAdjustmentCost(ArrayRef<Range> Indexed, ArrayRef<Range> Lexed,
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve2-intrinsics-fp-widening-mul-acc.ll21 ; FMLALB (Indexed)
52 ; FMLALT (Indexed)
83 ; FMLSLB (Indexed)
114 ; FMLSLT (Indexed)
H A Dsve2-intrinsics-widening-dsp.ll319 ; SMULLB (Indexed)
379 ; SMULLT (Indexed)
439 ; SQDMULLB (Indexed)
499 ; SQDMULLT (Indexed)
1035 ; UMULLB (Indexed)
1096 ; UMULLT (Indexed)
H A Dsve-intrinsics-int-arith.ll146 ; SDOT (Indexed)
302 ; UDOT (Indexed)
H A Dsve-intrinsics-fp-arith.ll199 ; FCMLA (Indexed)
562 ; FMLA (Indexed)
642 ; FMLS (Indexed)
759 ; FMUL (Indexed)
/llvm-project-15.0.7/llvm/lib/FuzzMutate/
H A DOperations.cpp256 Type *Indexed = ExtractValueInst::getIndexedType(Cur[0]->getType(), in validInsertValueIndex() local
258 return Indexed == Cur[1]->getType(); in validInsertValueIndex()
267 while (Type *Indexed = ExtractValueInst::getIndexedType(BaseTy, I)) { in validInsertValueIndex() local
268 if (Indexed == Cur[1]->getType()) in validInsertValueIndex()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DREADME_P9.txt19 - Vector Extract Unsigned Byte Left/Right-Indexed:
22 // Left-Indexed
27 // Right-Indexed
503 - Load/Store Vector Indexed: lxvx stxvx
527 - Load as Integer Byte/Halfword & Zero Indexed: lxsibzx lxsihzx
535 - Store as Integer Byte/Halfword Indexed: stxsibx stxsihx
543 - Load Vector Halfword*8/Byte*16 Indexed: lxvh8x lxvb16x
553 - Store Vector Halfword*8/Byte*16 Indexed: stxvh8x stxvb16x
571 - Load Vector Word & Splat Indexed: lxvwsx
H A DPPCScheduleP8.td158 // Update-Indexed form loads/stores are no longer first and last in the
H A DPPCInstrP10.td2233 // Indexed vector insert element
2267 // Indexed vector insert element
2280 // Indexed vector insert element
H A DPPCInstrVSX.td1673 // Load as Integer Byte/Halfword & Zero Indexed
1679 // Load Vector Halfword*8/Byte*16 Indexed
1683 // Load Vector Indexed
1694 // Load Vector Word & Splat Indexed
1711 // Store as Integer Byte/Halfword Indexed
1721 // Store Vector Halfword*8/Byte*16 Indexed
1725 // Store Vector Indexed
/llvm-project-15.0.7/llvm/test/MC/PowerPC/
H A Dvsx.s922 # Load as Integer Byte/Halfword & Zero Indexed
930 # Load Vector Halfword*8/Byte*16 Indexed
938 # Load Vector Indexed
951 # Load Vector Word & Splat Indexed
956 # Store as Integer Byte/Halfword Indexed
964 # Store Vector Halfword*8/Byte*16 Indexed
972 # Store Vector Indexed
H A Dppc64-encoding-vmx.s808 # Vector Extract Unsigned Left/Right-Indexed
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Datomics-indexed.ll10 ; Indexed version of loads
96 ; Indexed version of stores
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp5497 else if (kind == FMAInstKind::Indexed) in genFusedMultiply()
5609 FMAInstKind::Indexed); in genFusedMultiplyIdx()
6188 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6194 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6201 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6207 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6214 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6226 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6266 FMAInstKind::Indexed); in genAlternativeCodeSequence()
6278 FMAInstKind::Indexed); in genAlternativeCodeSequence()
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H A DSVEInstrFormats.td2152 // SVE Floating Point Multiply-Add - Indexed Group
2207 // SVE Floating Point Multiply - Indexed Group
2296 // SVE Floating Point Complex Multiply-Add - Indexed Group
2469 // SVE2 Floating Point Widening Multiply-Add - Indexed Group
3021 // SVE2 Integer Multiply-Add - Indexed Group
3071 // SVE2 Integer Multiply-Add Long - Indexed Group
3130 // SVE Integer Dot Product Group - Indexed Group
3228 // SVE2 Complex Integer Dot Product - Indexed Group
3276 // SVE2 Complex Multiply-Add - Indexed Group
3348 // SVE2 Integer Multiply - Indexed Group
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Darm64-memory.txt4 # Indexed loads
72 # Indexed stores
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-memory.s5 ; Indexed loads
78 ; Indexed stores
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7795 bool Indexed = AM != ISD::UNINDEXED; in getLoad() local
7798 SDVTList VTs = Indexed ? in getLoad()
8051 bool Indexed = AM != ISD::UNINDEXED; in getLoadVP() local
8145 bool Indexed = AM != ISD::UNINDEXED; in getStoreVP() local
8147 SDVTList VTs = Indexed ? getVTList(Ptr.getValueType(), MVT::Other) in getStoreVP()
8302 bool Indexed = AM != ISD::UNINDEXED; in getStridedLoadVP() local
8399 bool Indexed = AM != ISD::UNINDEXED; in getStridedStoreVP() local
8621 bool Indexed = AM != ISD::UNINDEXED; in getMaskedLoad() local
8622 assert((Indexed || Offset.isUndef()) && in getMaskedLoad()
8669 bool Indexed = AM != ISD::UNINDEXED; in getMaskedStore() local
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVScheduleV.td34 // 7.6. Vector Indexed Instructions
289 // 7.6. Vector Indexed Instructions
H A DRISCVInstrInfoV.td133 // Indexed Segment Loads and Stores
914 // Vector Indexed Instructions
1543 // Vector Indexed Instructions
1584 // Vector Indexed Segment Instructions
/llvm-project-15.0.7/mlir/docs/
H A DCAPI.md137 ### Indexed Components
/llvm-project-15.0.7/llvm/include/llvm/ProfileData/
H A DInstrProfData.inc652 /* Indexed profile format version (start from 1). */
/llvm-project-15.0.7/compiler-rt/include/profile/
H A DInstrProfData.inc652 /* Indexed profile format version (start from 1). */
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrFormats.td712 // Indexed Jump or Execute.

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