| /llvm-project-15.0.7/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 101 MachineOperand &Incr, unsigned BaseReg);
232 int64_t Incr; in tryToCombine() local
233 if (!isAddConstantOp(Add, Incr)) in tryToCombine()
235 if (!isValidLoadStoreOffset(Incr)) in tryToCombine()
262 fixPastUses(Uses, B, Incr); in tryToCombine()
354 MachineOperand &Incr, unsigned BaseReg) { in canFixPastUses() argument
356 assert(Incr.isImm() && "Expected immediate increment"); in canFixPastUses()
357 int64_t NewOffset = Incr.getImm(); in canFixPastUses()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 412 Register Incr = I->getOperand(2).getReg(); in expandAtomicBinOpSubword() local
444 .addReg(Incr); in expandAtomicBinOpSubword()
469 BuildMI(loopMBB, DL, TII->get(Mips::AND), Incr).addReg(Incr).addReg(Mask); in expandAtomicBinOpSubword()
476 .addReg(Incr); in expandAtomicBinOpSubword()
489 .addReg(Incr) in expandAtomicBinOpSubword()
503 .addReg(Incr) in expandAtomicBinOpSubword()
518 .addReg(Incr); in expandAtomicBinOpSubword()
525 .addReg(Incr) in expandAtomicBinOpSubword()
752 .addReg(Incr); in expandAtomicBinOp()
765 .addReg(Incr) in expandAtomicBinOp()
[all …]
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| H A D | MipsISelLowering.cpp | 1555 Register Incr = MI.getOperand(2).getReg(); in emitAtomicBinary() local
1596 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr)); in emitAtomicBinary()
1598 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr); in emitAtomicBinary()
1666 Register Incr = MI.getOperand(2).getReg(); in emitAtomicBinaryPartword() local
1804 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
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| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | IndVarSimplify.cpp | 228 auto *Incr = dyn_cast<BinaryOperator>(PN->getIncomingValue(BackEdge)); in handleFloatingPointIV() local
229 if (Incr == nullptr || Incr->getOpcode() != Instruction::FAdd) return false; in handleFloatingPointIV()
233 ConstantFP *IncValueVal = dyn_cast<ConstantFP>(Incr->getOperand(1)); in handleFloatingPointIV()
235 if (IncValueVal == nullptr || Incr->getOperand(0) != PN || in handleFloatingPointIV()
241 Value::user_iterator IncrUse = Incr->user_begin(); in handleFloatingPointIV()
243 if (IncrUse == Incr->user_end()) return false; in handleFloatingPointIV()
245 if (IncrUse != Incr->user_end()) return false; in handleFloatingPointIV()
372 Incr->getName()+".int", Incr); in handleFloatingPointIV()
390 Incr->replaceAllUsesWith(PoisonValue::get(Incr->getType())); in handleFloatingPointIV()
391 RecursivelyDeleteTriviallyDeadInstructions(Incr, TLI, MSSAU.get()); in handleFloatingPointIV()
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| H A D | LoopStrengthReduce.cpp | 2181 BinaryOperator *Incr = in OptimizeShadowIV() local
2183 if (!Incr) continue; in OptimizeShadowIV()
2184 if (Incr->getOpcode() != Instruction::Add in OptimizeShadowIV()
2185 && Incr->getOpcode() != Instruction::Sub) in OptimizeShadowIV()
2190 if (Incr->getOperand(0) == PH) in OptimizeShadowIV()
2191 C = dyn_cast<ConstantInt>(Incr->getOperand(1)); in OptimizeShadowIV()
2192 else if (Incr->getOperand(1) == PH) in OptimizeShadowIV()
2193 C = dyn_cast<ConstantInt>(Incr->getOperand(0)); in OptimizeShadowIV()
2209 BinaryOperator::Create(Incr->getOpcode() == Instruction::Add ? in OptimizeShadowIV()
2211 NewPH, CFP, "IV.S.next.", Incr); in OptimizeShadowIV()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVLIWPacketizer.cpp | 536 int Incr; in updateOffset() local
537 if (!HII->getIncrementValue(MJ, Incr)) in updateOffset()
541 if (!HII->isValidOffset(MI.getOpcode(), Offset+Incr, HRI)) in updateOffset()
544 MI.getOperand(OPI).setImm(Offset + Incr); in updateOffset()
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| /llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/ |
| H A D | DWARFDebugLineTest.cpp | 926 virtual uint64_t getAdjustedLine(uint64_t Base, uint64_t Incr) {
927 return Base + Incr;
1144 uint64_t getAdjustedLine(uint64_t Base, uint64_t Incr) override {
1146 ? AdjustAddressFixtureBase::getAdjustedLine(Base, Incr)
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.cpp | 418 int I = 0, End = NF, Incr = 1; in copyPhysReg() local
428 Incr = -1; in copyPhysReg()
431 for (; I != End; I += Incr) { in copyPhysReg()
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| H A D | RISCVISelLowering.h | 537 Value *AlignedAddr, Value *Incr,
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| H A D | RISCVISelLowering.cpp | 12134 IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
12145 Incr = Builder.CreateSExt(Incr, Builder.getInt64Ty()); in emitMaskedAtomicRMWIntrinsic()
12165 {AlignedAddr, Incr, Mask, SextShamt, Ordering}); in emitMaskedAtomicRMWIntrinsic()
12168 Builder.CreateCall(LrwOpScwLoop, {AlignedAddr, Incr, Mask, Ordering}); in emitMaskedAtomicRMWIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Frontend/OpenMP/ |
| H A D | OMPIRBuilder.cpp | 1964 Value *Incr = Step; in createCanonicalLoop() local
1976 Incr = Builder.CreateSelect(IsNeg, Builder.CreateNeg(Step), Step); in createCanonicalLoop()
1990 CountIfLooping = Builder.CreateAdd(Builder.CreateUDiv(Span, Incr), One); in createCanonicalLoop()
1994 Builder.CreateUDiv(Builder.CreateSub(Span, One), Incr), One); in createCanonicalLoop()
1996 InclusiveStop ? CmpInst::ICMP_ULT : CmpInst::ICMP_ULE, Span, Incr); in createCanonicalLoop()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 923 Value *Incr, Value *Mask,
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| H A D | PPCISelLowering.cpp | 18146 IRBuilderBase &Builder, AtomicRMWInst *AI, Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
18150 Type *ValTy = Incr->getType(); in emitMaskedAtomicRMWIntrinsic()
18155 Value *IncrLo = Builder.CreateTrunc(Incr, Int64Ty, "incr_lo"); in emitMaskedAtomicRMWIntrinsic()
18157 Builder.CreateTrunc(Builder.CreateLShr(Incr, 64), Int64Ty, "incr_hi"); in emitMaskedAtomicRMWIntrinsic()
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| /llvm-project-15.0.7/flang/lib/Semantics/ |
| H A D | resolve-names.cpp | 82 static char Incr(char ch);
1570 for (char ch = *fromLetter; ch; ch = ImplicitRules::Incr(ch)) { in SetTypeMapping()
1584 char ImplicitRules::Incr(char ch) { in Incr() function in Fortran::semantics::ImplicitRules
1600 for (char ch = 'a'; ch; ch = ImplicitRules::Incr(ch)) { in operator <<()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 3397 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
3401 Incr = -1; in copyPhysRegTuple()
3404 for (; SubReg != End; SubReg += Incr) { in copyPhysRegTuple()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1966 Value *AlignedAddr, Value *Incr, in emitMaskedAtomicRMWIntrinsic() argument
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| /llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/ |
| H A D | SLPVectorizer.cpp | 2762 int incrementUnscheduledDeps(int Incr) { in incrementUnscheduledDeps()
2765 UnscheduledDeps += Incr; in incrementUnscheduledDeps()
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