Searched refs:InOrderIssueStage (Results 1 – 7 of 7) sorted by relevance
46 InOrderIssueStage::InOrderIssueStage(const MCSubtargetInfo &STI, in InOrderIssueStage() function in llvm::mca::InOrderIssueStage52 unsigned InOrderIssueStage::getIssueWidth() const { in getIssueWidth()56 bool InOrderIssueStage::hasWorkToComplete() const { in hasWorkToComplete()115 bool InOrderIssueStage::canExecute(const InstRef &IR) { in canExecute()178 void InOrderIssueStage::notifyInstructionDispatched( in notifyInstructionDispatched()198 llvm::Error InOrderIssueStage::execute(InstRef &IR) { in execute()280 void InOrderIssueStage::updateIssuedInst() { in updateIssuedInst()311 void InOrderIssueStage::updateCarriedOver() { in updateCarriedOver()350 void InOrderIssueStage::notifyStallEvent() { in notifyStallEvent()381 llvm::Error InOrderIssueStage::cycleStart() { in cycleStart()[all …]
54 class InOrderIssueStage final : public Stage {82 InOrderIssueStage(const InOrderIssueStage &Other) = delete;83 InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;115 InOrderIssueStage(const MCSubtargetInfo &STI, RegisterFile &PRF,
19 Stages/InOrderIssueStage.cpp
82 auto InOrderIssue = std::make_unique<InOrderIssueStage>(STI, *PRF, CB, *LSU); in createInOrderPipeline()
27 "Stages/InOrderIssueStage.cpp",
986 In-order processors are modelled as a single ``InOrderIssueStage`` stage. It
5408 llvm/include/llvm/MCA/Stages/InOrderIssueStage.h6133 llvm/lib/MCA/Stages/InOrderIssueStage.cpp