Searched refs:InHi (Results 1 – 4 of 4) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1498 SDValue InLo, InHi; in SplitVecRes_ExtVecInRegOp() local
1501 GetSplitVector(N0, InLo, InHi); in SplitVecRes_ExtVecInRegOp()
1503 std::tie(InLo, InHi) = DAG.SplitVectorOperand(N, 0); in SplitVecRes_ExtVecInRegOp()
1524 InHi = DAG.getVectorShuffle(InLoVT, dl, InLo, DAG.getUNDEF(InLoVT), SplitHi); in SplitVecRes_ExtVecInRegOp()
1527 Hi = DAG.getNode(Opcode, dl, OutHiVT, InHi); in SplitVecRes_ExtVecInRegOp()
2639 SDValue InLo, InHi; in SplitVecRes_VECTOR_REVERSE() local
2640 GetSplitVector(N->getOperand(0), InLo, InHi); in SplitVecRes_VECTOR_REVERSE()
2643 Lo = DAG.getNode(ISD::VECTOR_REVERSE, DL, InHi.getValueType(), InHi); in SplitVecRes_VECTOR_REVERSE()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1232 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SubV}); in insertHvxSubvectorReg() local
1233 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg()
1279 SDValue InHi = DAG.getNode(ISD::CONCAT_VECTORS, dl, VecTy, {V0, SingleV}); in insertHvxSubvectorReg() local
1280 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo); in insertHvxSubvectorReg()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1282 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, in initAccumulator() local
1284 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); in initAccumulator()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 22271 SDValue InHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i16, In, in LowerTRUNCATE() local
22273 return DAG.getNode(X86ISD::PACKUS, DL, VT, InLo, InHi); in LowerTRUNCATE()
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