| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrFormats.td | 79 class I_16_ZX<string op, ImmLeaf ImmType, list<dag> pattern>
81 (outs GPR:$rz), (ins GPR:$rx,ImmType:$imm16),
93 class I_16_MOV<bits<5> sop, string op, ImmLeaf ImmType>
96 [(set GPR:$rz, ImmType:$imm16)]> {
197 class I_12<bits<4> sop, string op, SDNode node, ImmLeaf ImmType>
200 [(set GPR:$rz, (node GPR:$rx, ImmType:$imm12))]> {
264 class I_5_ZX<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
267 (ins CARRY:$cond, GPR:$false, GPR:$rx, ImmType:$imm5),
471 class I_5_X<bits<6> sop, bits<5> pcode, string op, ImmLeaf ImmType,
474 (outs CARRY:$ca), (ins GPR:$rx, ImmType:$imm5),
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrFormats.td | 83 class ImmType<bits<4> val> {
86 def NoImm : ImmType<0>;
87 def Imm8 : ImmType<1>;
88 def Imm8PCRel : ImmType<2>;
290 ImmType ImmT = i;
841 ImmType ImmT = Imm8;
845 ImmType ImmT = Imm8;
849 ImmType ImmT = Imm8;
853 ImmType ImmT = Imm8;
857 ImmType ImmT = Imm8;
[all …]
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| H A D | X86InstrArithmetic.td | 540 PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
568 ImmType ImmEncoding = immkind;
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoVPseudos.td | 2265 defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
2274 defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
2284 defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
2293 defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
2302 defm "" : VPseudoBinaryV_VI<ImmType, Constraint>,
2400 multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
2403 defm "" : VPseudoBinaryV_VI<ImmType>,
2651 defm "" : VPseudoVSLDV_VI<ImmType, Constraint>,
4296 ImmLeaf ImmType> {
4301 (vti.Scalar ImmType:$rs2),
[all …]
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| H A D | RISCVInstrInfoVSDPatterns.td | 123 Operand ImmType = simm5>
129 !cast<ComplexPattern>(SplatPat#_#ImmType),
130 ImmType>;
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| H A D | RISCVInstrInfoVVLPatterns.td | 376 Operand ImmType = simm5>
382 !cast<ComplexPattern>(SplatPat#_#ImmType),
383 ImmType>;
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| H A D | RISCVInstrInfo.td | 1129 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType>
1130 : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)),
1131 (Inst GPR:$rs1, ImmType:$imm)>;
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | FastISel.h | 376 MVT ImmType);
|
| /llvm-project-15.0.7/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXIntrinsics.td | 1922 NVPTXRegClass regclass, Operand ImmType,
1937 (ins Int32Regs:$src, ImmType:$b),
1940 (ins Int64Regs:$src, ImmType:$b),
1972 (ins Int32Regs:$src, ImmType:$b, ImmType:$c),
1975 (ins Int64Regs:$src, ImmType:$b, ImmType:$c),
1992 regclass, ImmType, Imm, ImmTy, Preds>;
2006 regclass, ImmType, Imm, ImmTy, Preds>;
2031 regclass, ImmType, Imm, ImmTy,
2034 regclass, ImmType, Imm, ImmTy,
2043 regclass, ImmType, Imm, ImmTy,
[all …]
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 1862 uint64_t Imm, MVT ImmType) { in fastEmit_ri_() argument
1883 Register MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm); in fastEmit_ri_()
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| /llvm-project-15.0.7/llvm/docs/TableGen/ |
| H A D | index.rst | 139 ImmType ImmT = NoImm;
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| H A D | ProgRef.rst | 1959 ImmType ImmT = NoImm;
|