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/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsX86.td920 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
927 [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
3094 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
3106 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
3451 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
3469 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
5042 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
5046 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
5050 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
5054 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>,
[all …]
H A DIntrinsicsHexagonDep.td1140 Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgInd…
1743 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgInde…
2829 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<Ar…
3171 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgI…
3177 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<Arg…
3183 Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<Arg…
3189 Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<Ar…
3480 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIn…
3486 Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgI…
3510 Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<Ar…
[all …]
H A DIntrinsicsMips.td305 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
308 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
358 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
361 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
365 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
586 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
589 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
592 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
595 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
612 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsAMDGPU.td433 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>], "",
448 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]
466 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>,
467 ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>, ImmArg<ArgIndex<7>>
1170 ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>, ImmArg<ArgIndex<6>>,
1347 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<6>>,
1362 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<6>>,
1374 [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>,
1914 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>],
2178 ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<5>>]
[all …]
H A DIntrinsicsARM.td285 …y, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmA…
288 …y, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmA…
294 …llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<…
298 …llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<…
303 …2_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgInde…
306 …2_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgInde…
310 … llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
312 … llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
315 … llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
317 … llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsSystemZ.td42 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
63 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
68 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
72 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
241 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
254 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
379 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
411 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
426 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
431 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsSPIRV.td21 …def int_spv_gep : Intrinsic<[llvm_anyptr_ty], [llvm_i1_ty, llvm_any_ty, llvm_vararg_ty], [ImmArg<A…
22 …sic<[llvm_i32_ty], [llvm_anyptr_ty, llvm_i16_ty, llvm_i8_ty], [ImmArg<ArgIndex<1>>, ImmArg<ArgInde…
23 …c<[], [llvm_any_ty, llvm_anyptr_ty, llvm_i16_ty, llvm_i8_ty], [ImmArg<ArgIndex<2>>, ImmArg<ArgInde…
H A DIntrinsics.td565 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
639 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
666 ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>;
734 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>,
1241 ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>,
1727 ImmArg<ArgIndex<2>>]>;
1780 [ImmArg<ArgIndex<2>>]>;
1783 [ImmArg<ArgIndex<2>>]>;
1874 ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
1881 NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>,
[all …]
H A DIntrinsicsRISCV.td164 ImmArg<ArgIndex<1>>,
165 ImmArg<ArgIndex<2>>]>;
170 ImmArg<ArgIndex<0>>,
171 ImmArg<ArgIndex<1>>]>;
180 ImmArg<ArgIndex<1>>,
181 ImmArg<ArgIndex<2>>]>;
186 ImmArg<ArgIndex<0>>,
187 ImmArg<ArgIndex<1>>]>;
443 [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
1542 ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsPowerPC.td564 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
567 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
570 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
573 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
602 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
605 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
1132 … llvm_i32_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
1136 … llvm_i32_ty, llvm_i32_ty], [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
1421 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
1668 [IntrNoMem, ImmArg<ArgIndex<0>>]>;
[all …]
H A DIntrinsicsHexagon.td54 [IntrArgMemOnly, ImmArg<ArgIndex<3>>]>;
60 [IntrWriteMem, ImmArg<ArgIndex<3>>]>;
66 [IntrWriteMem, ImmArg<ArgIndex<3>>]>;
263 ImmArg<ArgIndex<2>>]>;
283 ImmArg<ArgIndex<2>>],
315 ImmArg<ArgIndex<2>>]>;
339 ImmArg<ArgIndex<2>>],
H A DIntrinsicsAArch64.td769 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
777 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
887 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
1053 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
1061 [IntrNoMem, ImmArg<ArgIndex<3>>]>;
1109 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
1119 [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
1140 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
1178 [IntrNoMem, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
1313 [IntrNoMem, ImmArg<ArgIndex<2>>]>;
[all …]
H A DIntrinsicsWebAssembly.td92 [Throws, IntrNoReturn, ImmArg<ArgIndex<0>>]>;
107 [IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
113 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
H A DIntrinsicsBPF.td25 [IntrNoMem, ImmArg<ArgIndex<1>>]>;
H A DAttributes.td223 def ImmArg : EnumAttr<"immarg", [ParamAttr]>;
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dimmarg.td7 def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
8 def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
H A DGlobalISelEmitter-SDNodeXForm-timm.td14 def int_mytarget_sleep : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
15 def int_mytarget_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<1>>, I…
H A Dimmarg-predicated.td7 def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
H A DGlobalISelEmitter-immarg-literal-pattern.td6 def int_mytarget_sleep : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
/llvm-project-15.0.7/llvm/utils/TableGen/
H A DCodeGenIntrinsics.h161 ImmArg, enumerator
H A DCodeGenTarget.cpp910 ArgumentAttributes.emplace_back(ArgNo, ImmArg, 0); in setProperty()
928 ArgAttribute Val{ParamIdx + 1, ImmArg, 0}; in isParamImmArg()
H A DIntrinsicEmitter.cpp736 case CodeGenIntrinsic::ImmArg: in EmitAttributes()
/llvm-project-15.0.7/llvm/lib/Target/SPIRV/
H A DSPIRVEmitIntrinsics.cpp401 (II->paramHasAttr(OpNo, Attribute::ImmArg)))) in processInstrAfterVisit()
/llvm-project-15.0.7/llvm/docs/
H A DExtendingLLVM.rst53 must be indicated with the ImmArg property. Note that any intrinsic
/llvm-project-15.0.7/llvm/lib/IR/
H A DVerifier.cpp1766 if (Attrs.hasAttribute(Attribute::ImmArg)) { in verifyParameterAttrs()
1955 Check(!ArgAttrs.hasAttribute(Attribute::ImmArg), in verifyFunctionAttrs()
3250 if (Attrs.hasParamAttr(i, Attribute::ImmArg)) { in visitCallBase()
3253 Check(Callee && Callee->hasParamAttribute(i, Attribute::ImmArg), in visitCallBase()
3258 if (Call.paramHasAttr(i, Attribute::ImmArg)) { in visitCallBase()

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