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/llvm-project-15.0.7/mlir/test/Interfaces/TilingInterface/
H A Dtile-and-fuse-using-interface.mlir22 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
25 // CHECK-DAG: %[[RHS_TILE:.+]] = tensor.extract_slice %[[ARG1]][0, %[[IV1]]]
67 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
70 // CHECK-DAG: %[[RHS_TILE:.+]] = tensor.extract_slice %[[ARG1]][0, %[[IV1]]]
77 // CHECK-DAG: %[[BIAS_TILE:.+]] = tensor.extract_slice %[[ARG2]][%[[IV1]]]
170 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
217 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] =
269 // CHECK: %[[YIELD:.+]] = scf.for %[[IV1:[a-zA-Z0-9_]+]]
288 // CHECK-SAME: into %[[ARG6]][%[[IV0]], %[[IV1]]]
326 // CHECK: %[[YIELD:.+]] = scf.for %[[IV1:[a-zA-Z0-9_]+]]
[all …]
H A Dtile-using-interface.mlir28 // CHECK: %[[TS_X:.+]] = affine.min #[[MAP1]](%[[IV1]])[%[[C20]], %[[N]]]
32 // CHECK-SAME: [0, %[[IV1]]] [%[[K]], %[[TS_X]]] [1, 1]
34 // CHECK-SAME: [%[[IV0]], %[[IV1]]] [%[[TS_Y]], %[[TS_X]]] [1, 1]
39 // CHECK-SAME: [%[[IV0]], %[[IV1]]] [%[[TS_Y]], %[[TS_X]]] [1, 1]
70 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] = %[[C0]] to %[[N]] step %[[C20]]
71 // CHECK: %[[TS_N:.+]] = affine.min #[[MAP1]](%[[IV1]])[%[[C20]], %[[N]]]
77 // CHECK-SAME: [%[[IV2]], %[[IV1]]] [%[[TS_K]], %[[TS_N]]] [1, 1]
79 // CHECK-SAME: [%[[IV0]], %[[IV1]]] [%[[TS_M]], %[[TS_N]]] [1, 1]
175 // CHECK: scf.for %[[IV1:[a-zA-Z0-9]+]] = %[[C0]] to %[[Q]] step %[[C20]]
264 // CHECK-SAME: [%[[IV2]], %[[IV1]]] [%[[TS_M]], %[[TS_K]]] [1, 1]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Affine/
H A Dunroll-jam.mlir76 // UJAM-FOUR-NEXT: affine.for [[IV1:%arg[0-9]+]] = 1 to 100 {
114 // CHECK-NEXT: affine.for [[IV1:%arg[0-9]+]] = 0 to %[[K]] {
115 // CHECK-NEXT: "test.foo"([[IV0]], [[IV1]])
133 // CHECK-NEXT: "addi32"([[IV1]], [[IV1]])
159 // CHECK-NEXT: [[RES4:%[0-9]+]] = "bar"([[IV0]], [[IV1]], [[ACC1]])
161 // CHECK-NEXT: [[RES5:%[0-9]+]] = "bar"([[INC1]], [[IV1]], [[ACC2]])
204 // CHECK-NEXT: [[RES4:%[0-9]+]] = "bar"([[IV0]], [[IV1]], [[ACC0]])
205 // CHECK-NEXT: [[RES5:%[0-9]+]] = "bar1"([[IV0]], [[IV1]], [[ACC1]])
207 // CHECK-NEXT: [[RES6:%[0-9]+]] = "bar"([[INC1]], [[IV1]], [[ACC2]])
247 // CHECK-NEXT: [[RES4:%[0-9]+]] = "bar"([[IV0]], [[IV1]], [[ACC1]])
[all …]
H A Daffine-data-copy.mlir218 // CHECK: affine.for %[[IV1:.*]] = 0 to 4096 step 100
220 …K-NEXT: affine.for %[[IV2:.*]] = #[[$MAP_IDENTITY]](%[[IV1]]) to min #[[$MAP_MIN_UB1]](%[[IV1]])…
222 // CHECK-NEXT: affine.store %{{.*}}, %[[BUF]][%[[IV2]] - %[[IV1]]] : memref<100xf32>
224 …K-NEXT: affine.for %[[IV2:.*]] = #[[$MAP_IDENTITY]](%[[IV1]]) to min #[[$MAP_MIN_UB2]](%[[IV1]])…
225 // CHECK-NEXT: affine.load %[[BUF]][-%[[IV1]] + %[[IV2]]] : memref<100xf32>
227 // CHECK-NEXT: affine.store %{{.*}}, %[[BUF]][-%[[IV1]] + %[[IV2]]] : memref<100xf32>
229 …K: affine.for %[[IV2:.*]] = #[[$MAP_IDENTITY]](%[[IV1]]) to min #[[$MAP_MIN_UB1]](%[[IV1]])…
230 // CHECK-NEXT: affine.load %[[BUF]][%[[IV2]] - %[[IV1]]] : memref<100xf32>
H A Daffine-loop-normalize.mlir59 // CHECK-DAG: [[$IV1:#map[0-9]+]] = affine_map<(d0) -> (d0 * 3)>
65 // CHECK-NEXT: %[[IIIV:.*]] = affine.apply [[$IV1]](%[[II]])
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnroll/ARM/
H A Dloop-unrolling.ll17 ; CHECK-NOUNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
18 ; CHECK-NOUNROLL: [[IV2]] = add nuw nsw i32 [[IV1]], 1
23 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
24 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
68 ; CHECK-NOUNROLL: [[IV2]] = add nuw i32 [[IV1]], 1
72 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
120 ; CHECK-NOUNROLL: [[IV1]] = add nuw i32 [[IV0]], 1
162 ; CHECK-NOUNROLL: [[IV1]] = add nuw nsw i32 [[IV0]], 1
163 ; CHECK-NOUNROLL: icmp eq i32 [[IV1]], 1024
167 ; CHECK-UNROLL: [[IV1]] = add nuw nsw i32 [[IV0]], 1
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtile-to-foreach-thread.mlir61 // CHECK: scf.foreach_thread (%[[IV0:.+]], %[[IV1:.+]]) in (%[[c10]], %[[c21]])
62 // CHECK: %[[TSMIN:.+]] = affine.min #[[$map0]](%[[IV1]])
68 // CHECK: %[[LB1:.+]] = affine.apply #[[$map3]](%[[IV1]])
71 // CHECK: %[[LB1:.+]] = affine.apply #[[$map3]](%[[IV1]])
111 // CHECK: scf.foreach_thread (%[[IV0:.+]], %[[IV1:.+]]) in (%[[NT0]], %[[NT1]])
113 // CHECK: %[[TS1:.+]] = affine.min #[[$map4]](%[[IV1]])[%[[N]]]
116 // CHECK: %[[LB1:.+]] = affine.apply #[[$map6]](%[[IV1]])
119 // CHECK: %[[LB1:.+]] = affine.apply #[[$map6]](%[[IV1]])
154 // CHECK: %[[TS:.+]] = affine.min #[[$map0]](%[[IV1]])
159 // CHECK: %[[LB1:.+]] = affine.apply #[[$map3]](%[[IV1]])
[all …]
H A Dparallel-loops.mlir57 // CHECK: scf.parallel (%[[IV0:.*]], %[[IV1:.*]]) = (%[[C0]], %[[C0]]) to (%[[D0]], %[[D1]]) …
60 // CHECK: memref.load %{{.*}}[%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]]]
61 // CHECK: store %{{.*}}, %{{.*}}[%[[IV0]], %[[IV1]], %[[IV3]]]
92 // CHECK: scf.parallel (%[[IV0:.*]], %[[IV1:.*]]) = (%[[C0]], %[[C0]]) to (%[[D0]], %[[D1]]) …
96 // CHECK: memref.load %{{.*}}[%[[IV0]], %[[IV1]], %[[IV2]], %[[IV3]], %[[IV4]], %[[IV5]…
97 // CHECK: store %{{.*}}, %{{.*}}[%[[IV0]], %[[IV1]], %[[IV4]], %[[IV3]]]
H A Dtile-and-fuse-tensors.mlir117 // CHECK-NEXT: scf.for %[[IV1:.+]] = %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[ARG1:.+]] = %[[…
118 // CHECK-NEXT: %[[OFFSET_W:.+]] = affine.apply #[[MAP0]](%[[IV1]])
131 // CHECK: tensor.insert_slice %[[ADD]] into %[[ARG2]][0, %[[IV0]], %[[IV1]], %[[IV2]]] […
234 // CHECK-NEXT: scf.for %[[IV1:.+]] = %{{.+}} to %[[ELEM_OH]]
235 // CHECK-NEXT: %[[SIZE_ELEM_OH:.+]] = affine.min #[[BOUND16_MAP]](%[[IV1]])[%[[ELEM_OH]]]
236 // CHECK-NEXT: %[[OFFSET_OH:.+]] = affine.apply #[[X2_MAP]](%[[IV1]])
238 // CHECK-NEXT: %[[SIZE_ELEM_OH_2:.+]] = affine.min #[[BOUND16_MAP_2]](%[[IV1]])[%[[FILL_H]], …
248 // CHECK-NEXT: %[[ST_ELEM:.+]] = tensor.extract_slice %[[ELEM]][%[[IV0]], %[[IV1]], %[[IV…
250 // CHECK-NEXT: %[[ST_ARG:.+]] = tensor.extract_slice %[[ARG]][%[[IV0]], %[[IV1]], %[[IV2]…
255 // CHECK-NEXT: %[[ST_FILL:.+]] = tensor.extract_slice %[[FILL]][%[[IV0]], %[[IV1]], %[[IV…
[all …]
H A Dtile-scalarize-dynamic-dims.mlir12 // CHECK: scf.for %[[IV1:.*]] = %[[C0]] to %[[UB2]] step %[[C1]]
13 // CHECK: %[[S1:.*]] = tensor.extract_slice %[[ARG0]][%[[IV0]], %[[IV1]]] [1, 1] [1, 1]…
14 // CHECK: %[[S2:.*]] = tensor.extract_slice %[[ARG1]][%[[IV1]], 0] [1, 2000] [1, 1] : t…
H A Dtransform-op-fuse.mlir70 // CHECK: scf.for %[[IV1:.+]] = %{{.+}} to %{{.+}} step %[[C7]] iter_args(%[[FOR_ARG1:.+]] …
71 // CHECK: %[[OUT_SLICE0:.+]] = tensor.extract_slice %[[FOR_ARG1]][%[[IV0]], %[[IV1]]]
H A Dtile-tensors.mlir97 // CHECK: scf.for %[[IV1:[0-9a-zA-Z]*]] =
102 // CHECK: %[[OFF1:.*]] = affine.apply #[[MAP2]](%[[IV1]]
H A Dfuse-with-reshape-by-collapsing.mlir97 // CHECK: %[[IV1:.+]] = linalg.index 1
98 // CHECK: %[[REM_IV1:.+]] = arith.remui %[[IV1]], %[[C4]]
99 // CHECK: %[[DIV_IV1:.+]] = arith.divui %[[IV1]], %[[C4]]
219 // CHECK: %[[IV1:.+]] = linalg.index 3
220 // CHECK: %[[REM1_IV1:.+]] = arith.remui %[[IV1]], %[[D0]]
221 // CHECK: %[[DIV1_IV1:.+]] = arith.divui %[[IV1]], %[[D0]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dunroll-in-loop-vectorizer.ll14 ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[IV1:%.*]], [[LOOP]] ], [ 0, [[LOOP_PREHEADER]] ]
19 ; CHECK-NEXT: [[IV1]] = add i32 [[IV]], 1
20 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV1]], [[SIZE]]
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dloop-unroll.mlir107 // UNROLL-OUTER-BY-2-NEXT: scf.for %[[IV1:.*]] = %[[LB1]] to %[[UB1]] step %[[STEP1]] {
108 // UNROLL-OUTER-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[IV1]]] : memref<?xf32>
110 // UNROLL-OUTER-BY-2-NEXT: scf.for %[[IV1:.*]] = %[[LB1]] to %[[UB1]] step %[[STEP1]] {
111 // UNROLL-OUTER-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[IV1]]] : memref<?xf32>
115 // UNROLL-OUTER-BY-2-NEXT: scf.for %[[IV1:.*]] = %[[LB1]] to %[[UB1]] step %[[STEP1]] {
116 // UNROLL-OUTER-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[IV1]]] : memref<?xf32>
142 // UNROLL-INNER-BY-2: scf.for %[[IV1:.*]] = %[[LB1]] to %{{.*}} step %{{.*}} {
143 // UNROLL-INNER-BY-2-NEXT: memref.store %{{.*}}, %[[MEM]][%[[IV1]]] : memref<?xf32>
146 // UNROLL-INNER-BY-2-NEXT: %[[V1:.*]] = arith.addi %[[IV1]], %[[V0]] : index
149 // UNROLL-INNER-BY-2-NEXT: scf.for %[[IV1:.*]] = %{{.*}} to %[[UB1]] step %[[STEP1]] {
[all …]
H A Dloop-pipelining.mlir17 // CHECK-NEXT: %[[IV1:.*]] = arith.addi %[[IV]], %[[C1]] : index
18 // CHECK-NEXT: %[[LR:.*]] = memref.load %[[A]][%[[IV1]]] : memref<?xf32>
54 // CHECK-NEXT: %[[IV1:.*]] = arith.addi %[[IV]], %[[C6]] : index
55 // CHECK-NEXT: %[[LR:.*]] = memref.load %[[A]][%[[IV1]]] : memref<?xf32>
285 // CHECK-NEXT: %[[IV1:.*]] = arith.addi %[[IV]], %[[C1]] : index
286 // CHECK-NEXT: %[[L1:.*]] = memref.load %[[A]][%[[IV1]]] : memref<?xf32>
359 // CHECK-NEXT: %[[IV1:.*]] = arith.addi %[[IV]], %[[C1]] : index
360 // CHECK-NEXT: %[[L2:.*]] = memref.load %[[A]][%[[IV1]]] : memref<?xf32>
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dreduction-odd-interleave-counts.ll11 ; UF3-NEXT: [[IV1:%.+]] = add i64 [[IV]], 4
14 ; UF3-NEXT: [[GEP1:%.+]] = getelementptr inbounds i32, i32* %A, i64 [[IV1]]
46 ; UF5-NEXT: [[IV1:%.+]] = add i64 [[IV]], 4
51 ; UF5-NEXT: [[GEP1:%.+]] = getelementptr inbounds i32, i32* %A, i64 [[IV1]]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/AArch64/
H A Dhoisting-sinking-required-for-vectorization.ll180 ; CHECK-NEXT: [[IV1:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ], [ 0, [[ENTRY:%.*]] ]
181 ; CHECK-NEXT: [[C_GEP:%.*]] = getelementptr inbounds i32, i32* [[C]], i64 [[IV1]]
184 ; CHECK-NEXT: [[A_GEP_0:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[IV1]]
187 ; CHECK-NEXT: [[B_GEP_0:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[IV1]]
196 ; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV1]], 1
197 ; CHECK-NEXT: [[CMP_0:%.*]] = icmp ult i64 [[IV1]], 9999
/llvm-project-15.0.7/mlir/test/Transforms/
H A Dnormalize-memrefs.mlir87 // CHECK: affine.for %[[IV1:.*]] =
89 // CHECK: affine.load %{{.*}}[%[[IV0]] * 2, %[[IV1]] * 4] : memref<127x509xf32>
103 // CHECK: affine.for %[[IV1:.*]] =
105 // CHECK: affine.load %{{.*}}[%[[IV0]] * 3 + %[[IV1]] * 17] : memref<72xf32>
/llvm-project-15.0.7/mlir/test/Dialect/Affine/SuperVectorize/
H A Dvectorize_1d.mlir171 // CHECK-NEXT: affine.for %[[IV1:[arg0-9]+]] = 0 to 32 {
172 // CHECK-NEXT: %[[BROADCAST:.*]] = vector.broadcast %[[IV1]] : index to vector<128xindex>
174 …// CHECK-NEXT: vector.transfer_write %[[CAST]], {{.*}}[%[[IV1]], %[[IV0]]] : vector<128xi32>, …
194 // CHECK-NEXT: affine.for %[[IV1:[arg0-9]+]] = 0 to 512 step 128 {
195 // CHECK-NOT: vector.broadcast %[[IV1]]
198 // CHECK-NEXT: %[[INDEX1:.*]] = affine.apply #[[$map0]](%[[IV0]], %[[IV2]], %[[IV1]])
199 // CHECK-NEXT: %[[INDEX2:.*]] = affine.apply #[[$map1]](%[[IV0]], %[[IV2]], %[[IV1]])
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsimple_phi_condition.ll82 ; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[IF_TRUE]] ], [ [[IV1_NEXT:%.*]], [[LOOP1]] ]
83 ; CHECK-NEXT: [[IV1_NEXT]] = add i32 [[IV1]], 1
123 ; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[IF_TRUE]] ], [ [[IV1_NEXT:%.*]], [[LOOP1]] ]
124 ; CHECK-NEXT: [[IV1_NEXT]] = add i32 [[IV1]], 1
/llvm-project-15.0.7/clang/test/ARCMT/
H A Dobjcmt-protocol-conformance.m34 id IV1; field
H A Dobjcmt-protocol-conformance.m.result34 id IV1;
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dlftr-multi-exit.ll443 ; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV1_NEXT:%.*]], [[OUTER_LATCH:%.*]…
444 ; CHECK-NEXT: store volatile i32 [[IV1]], i32* @A, align 4
445 ; CHECK-NEXT: [[IV1_NEXT]] = add nuw nsw i32 [[IV1]], 1
/llvm-project-15.0.7/llvm/test/Transforms/LoopDeletion/
H A Dnoop-loops-with-subloops.ll308 ; CHECK-NEXT: [[IV1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV1_NEXT:%.*]], [[LOOP1_LATCH:%.*]…
324 ; CHECK-NEXT: [[IV1_NEXT]] = add nuw i32 [[IV1]], 1

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