| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | invalid-barrier.s | 22 @ ISB
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| H A D | basic-arm-instructions.s | 1058 @ ISB
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| H A D | basic-thumb2-instructions.s | 823 @ ISB
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | intrinsics-memory-barrier.ll | 40 ; And ISB.
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | intrinsics-memory-barrier.ll | 43 ; And ISB.
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| /llvm-project-15.0.7/llvm/lib/ProfileData/ |
| H A D | InstrProfWriter.cpp | 336 InstrProfSummaryBuilder ISB(ProfileSummaryBuilder::DefaultCutoffs); in writeImpl() local
337 InfoObj->SummaryBuilder = &ISB; in writeImpl()
468 std::unique_ptr<ProfileSummary> PS = ISB.getSummary(); in writeImpl()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64InstPrinter.cpp | 1511 if (Opcode == AArch64::ISB) { in printBarrierOption()
1512 auto ISB = AArch64ISB::lookupISBByEncoding(Val); in printBarrierOption() local
1513 Name = ISB ? ISB->Name : ""; in printBarrierOption()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 222 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ISB)).addImm(0xf); in insertFullSpeculationBarrier()
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| H A D | AArch64SchedCyclone.td | 295 // ISB
296 def : InstRW<[WriteI], (instrs ISB)>;
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| H A D | AArch64AsmPrinter.cpp | 1329 TmpInstISB.setOpcode(AArch64::ISB); in emitInstruction()
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| H A D | AArch64SystemOperands.td | 193 // ISB (instruction-fetch barrier) instruction options.
196 class ISB<string name, bits<4> encoding> : SearchableTable{
205 def : ISB<"sy", 0xf>;
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| H A D | AArch64SchedFalkorDetails.td | 1245 def : InstRW<[FalkorWr_1none_0cyc], (instrs BRK, DCPS1, DCPS2, DCPS3, HINT, HLT, HVC, ISB, SMC, S…
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| H A D | AArch64SchedKryoDetails.td | 477 (instrs BRK, DCPS1, DCPS2, DCPS3, HLT, HVC, ISB, HINT, SMC, SVC)>;
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| H A D | AArch64InstrInfo.cpp | 1093 case AArch64::ISB: in isSchedulingBoundary()
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| H A D | AArch64InstrInfo.td | 950 def ISB : CRmSystemI<barrier_op, 0b110, "isb",
1431 def : InstAlias<"isb", (ISB 0xf)>;
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 418 struct ISB : SysAlias { struct
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 2246 TmpInstISB.setOpcode(ARM::ISB); in emitInstruction()
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| H A D | ARMScheduleA57.td | 119 "(t2|t)?HINT$", "(t)?HLT$", "(t2)?HVC$", "(t2)?ISB$", "ITasm$",
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| H A D | ARMInstrInfo.td | 5119 // ISB has only full system option
5120 def ISB : AInoP<(outs), (ins instsyncb_opt:$opt), MiscFrm, NoItinerary,
6203 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | basic-arm-instructions.txt | 652 # ISB
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| H A D | thumb2.txt | 449 # ISB
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