ISA (reference) in projects: llvm-project-15.0.7

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Searched refs:ISA (Results 1 – 25 of 174) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A D	divergent-branch-uniform-condition.ll	`19 ; ISA-LABEL: main: 20 ; ISA: ; %bb.0: ; %start 22 ; ISA-NEXT: s_mov_b32 m0, s0 23 ; ISA-NEXT: s_mov_b32 s8, 0 29 ; ISA-NEXT: s_branch .LBB0_3 30 ; ISA-NEXT: .LBB0_1: ; %Flow1 35 ; ISA-NEXT: .LBB0_2: ; %Flow 44 ; ISA-NEXT: .LBB0_3: ; %loop 59 ; ISA-NEXT: .LBB0_6: ; %Flow2 63 ; ISA-NEXT: ; %bb.7: ; %if1 [all …]`
H A D	elf-notes.ll	`19 ; OSABI-UNK-ELF: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) 20 ; OSABI-UNK-ELF: AMD HSA ISA Name: 35 ; OSABI-HSA-ELF: NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version) 36 ; OSABI-HSA-ELF: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) 37 ; OSABI-HSA-ELF: AMD HSA ISA Name: 61 ; OSABI-PAL-ELF: NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version) 62 ; OSABI-PAL-ELF: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) 63 ; OSABI-PAL-ELF: AMD HSA ISA Name:`
H A D	README	`9 ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g. 20 the file is named after a DAG opcode or ISA instruction that has an`
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A D	cpus.ll	`5 ; GENERIC: ISA: MIPS32 9 ; MIPS1: ISA: MIPS1 12 ; MIPS2: ISA: MIPS2 15 ; MIPS3: ISA: MIPS3 18 ; MIPS4: ISA: MIPS4 22 ; MIPS32: ISA: MIPS32 25 ; MIPS32R2: ISA: MIPS32r2 28 ; MIPS32R3: ISA: MIPS32r3 31 ; MIPS32R5: ISA: MIPS32r5 38 ; MIPS64: ISA: MIPS64 [all …]`
/llvm-project-15.0.7/llvm/unittests/Analysis/
H A D	VectorFunctionABITest.cpp	47 VFISAKind &ISA = Info.ISA; member in __anon36cf3bb40111::VFABIParserTest 225 EXPECT_EQ(ISA, VFISAKind::SVE); in TEST_F() 234 EXPECT_EQ(ISA, VFISAKind::SVE); in TEST_F() 272 TEST_F(VFABIParserTest, ISA) { in TEST_F() argument 280 EXPECT_EQ(ISA, VFISAKind::SVE); in TEST_F() 283 EXPECT_EQ(ISA, VFISAKind::SSE); in TEST_F() 286 EXPECT_EQ(ISA, VFISAKind::AVX); in TEST_F() 374 EXPECT_EQ(ISA, VFISAKind::SVE); in TEST_F() 380 EXPECT_EQ(ISA, VFISAKind::SSE); in TEST_F() 386 EXPECT_EQ(ISA, VFISAKind::AVX); in TEST_F() [all …]
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A D	amdgpu-ieee.cl	`12 // Check AMDGCN ISA generation. 15 // RUN: \| FileCheck -check-prefixes=ISA-ON %s 18 // RUN: \| FileCheck -check-prefixes=ISA-OFF %s 26 // ISA-ON: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} 27 // ISA-ON: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} 28 // ISA-ON: v_min_f32_e32 29 // ISA-ON: ; IeeeMode: 1 30 // ISA-OFF-NOT: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} 31 // ISA-OFF-NOT: v_mul_f32_e64 v{{[0-9]+}}, 1.0, s{{[0-9]+}} 32 // ISA-OFF: v_min_f32_e32 [all …]`
H A D	builtins-amdgcn-raytracing.cl	`5 // RUN: -cl-std=CL2.0 -o - %s \| FileCheck -check-prefix=ISA %s 23 // ISA: image_bvh_intersect_ray 33 // ISA: image_bvh_intersect_ray 43 // ISA: image_bvh_intersect_ray 53 // ISA: image_bvh_intersect_ray`
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A D	invalid-mips4.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 32 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 34 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 36 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 38 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 40 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 42 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
H A D	invalid-mips5.s	10 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 50 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 52 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 54 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 56 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 58 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 60 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A D	note-amd-invalid-v2.test	61 # LLVM-NEXT: AMD HSA ISA Version: Invalid AMD HSA ISA Version 72 # LLVM-NEXT: AMD HSA ISA Version: Invalid AMD HSA ISA Version 83 # LLVM-NEXT: AMD HSA ISA Version: Invalid AMD HSA ISA Version 94 # LLVM-NEXT: AMD HSA ISA Version: Invalid AMD HSA ISA Version 137 # GNU-NEXT: AMD HSA ISA Version: 138 # GNU-NEXT: Invalid AMD HSA ISA Version 143 # GNU-NEXT: AMD HSA ISA Version: 144 # GNU-NEXT: Invalid AMD HSA ISA Version 149 # GNU-NEXT: AMD HSA ISA Version: 150 # GNU-NEXT: Invalid AMD HSA ISA Version [all …]
H A D	note-amd-valid-v2.test	41 # LLVM-NEXT: Type: NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version) 74 # LLVM-NEXT: Type: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) 75 # LLVM-NEXT: AMD HSA ISA Name: 85 # LLVM-NEXT: Type: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) 86 # LLVM-NEXT: AMD HSA ISA Name: abcdef 116 # GNU-NEXT: AMD 0x0000001b NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version) 117 # GNU-NEXT: AMD HSA ISA Version: 134 # GNU-NEXT: AMD 0x00000000 NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) 135 # GNU-NEXT: AMD HSA ISA Name: 140 # GNU-NEXT: AMD 0x00000006 NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name) [all …]
H A D	mips-abiflags.test	19 # GNU-NEXT:ISA: MIPS32r102 24 # GNU-NEXT:ISA Extension: Broadcom SB-1 36 # LLVM-NEXT: ISA: MIPS32r102 37 # LLVM-NEXT: ISA Extension: Broadcom SB-1 (0xC) 63 ISA: [[ISA=MIPS32]] 101 # RUN: llvm-readelf -A %t.isa1 \| FileCheck %s --check-prefix=CHECK-ISA -DVAL=MIPS1 102 # RUN: llvm-readobj -A %t.isa1 \| FileCheck %s --check-prefix=CHECK-ISA -DVAL=MIPS1 104 # CHECK-ISA: ISA: [[VAL]]{{$}} 107 # RUN: llvm-readelf -A %t.isa2 \| FileCheck %s --check-prefix=CHECK-ISA -DVAL=MIPS2 108 # RUN: llvm-readobj -A %t.isa2 \| FileCheck %s --check-prefix=CHECK-ISA -DVAL=MIPS2 [all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A D	invalid-mips5-wrong-error.s	38 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 40 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 42 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 44 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 46 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 48 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 50 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 52 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 54 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 56 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A D	invalid-mips32.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 47 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 49 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 51 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 53 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 55 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 57 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 59 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 61 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 63 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
H A D	invalid-mips32r2.s	9 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 15 …7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 17 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 19 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 21 …2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 23 …7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 25 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 27 …6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 29 …4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 31 …8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
H A D	invalid-mips5.s	10 … # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 85 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 87 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 89 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 91 …$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 93 …$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 95 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 97 …$f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 99 …$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level 101 …$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level [all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A D	Mips.td	`32 // Predicates for the instruction group membership such as ISA's. 106 "Mips4", "MIPS IV ISA Support", 116 "Mips32 ISA Support", 120 "Mips32r2", "Mips32r2 ISA Support", 124 "Mips32r3", "Mips32r3 ISA Support", 127 "Mips32r5", "Mips32r5 ISA Support", 131 "Mips32r6 ISA Support [experimental]", 135 "Mips64", "Mips64 ISA Support", 138 "Mips64r2", "Mips64r2 ISA Support", 141 "Mips64r3", "Mips64r3 ISA Support", [all …]`
/llvm-project-15.0.7/lld/test/ELF/
H A D	mips-elf-flags.s	`54 # SO-NEXT: ISA: MIPS32 55 # SO-NEXT: ISA Extension: None 75 # EXE-NEXT: ISA: MIPS32 76 # EXE-NEXT: ISA Extension: None 96 # EXE-R2-NEXT: ISA: MIPS32r2 97 # EXE-R2-NEXT: ISA Extension: None 117 # EXE-R5-NEXT: ISA: MIPS32r5 139 # EXE-R6-NEXT: ISA: MIPS32 161 # OCTEON-NEXT: ISA: MIPS64r2 183 # MICRO-NEXT: ISA: MIPS32 [all …]`
H A D	mips-fp-flags-err.test	`43 ISA: MIPS64 62 ISA: MIPS64 81 ISA: MIPS64 100 ISA: MIPS64 119 ISA: MIPS64 138 ISA: MIPS64 157 ISA: MIPS64`
H A D	mips-elf-flags-err.s	`2 # Check MIPS ELF ISA flag calculation if input files have different ISAs. 28 # Check that lld take in account EF_MIPS_MACH_XXX ISA flags 49 # R3R32: error: incompatible target ISA: 53 # R6OCTEON: error: incompatible target ISA:`
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A D	M68k.td	`23 "Is M68000 ISA supported">; 27 "Is M68010 ISA supported", 32 "Is M68020 ISA supported", 37 "Is M68030 ISA supported", 42 "Is M68040 ISA supported", 47 "Is M68060 ISA supported",`
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A D	mips_abi_flags_xx.s	`46 # CHECK-OBJ-32R1-NEXT: ISA: {{MIPS32$}} 47 # CHECK-OBJ-32R6-NEXT: ISA: MIPS32r6 48 # CHECK-OBJ-64R2-NEXT: ISA: MIPS64r2 49 # CHECK-OBJ-MIPS-NEXT: ISA Extension: None (0x0) 50 # CHECK-OBJ-OCTEON-NEXT: ISA Extension: Cavium Networks Octeon (0x5) 51 # CHECK-OBJ-OCTEONP-NEXT: ISA Extension: Cavium Networks OcteonP (0x3)`
/llvm-project-15.0.7/llvm/lib/Analysis/
H A D	VFABIDemangling.cpp	25 ParseRet tryParseISA(StringRef &MangledName, VFISAKind &ISA) { in tryParseISA() argument 31 ISA = VFISAKind::LLVM; in tryParseISA() 33 ISA = StringSwitch<VFISAKind>(MangledName.take_front(1)) in tryParseISA() 331 VFISAKind ISA; in tryDemangleForVFABI() local 332 if (tryParseISA(MangledName, ISA) != ParseRet::OK) in tryDemangleForVFABI() 405 if (ISA == VFISAKind::LLVM && VectorName == OriginalName) in tryDemangleForVFABI() 455 return VFInfo({Shape, std::string(ScalarName), std::string(VectorName), ISA}); in tryDemangleForVFABI()
/llvm-project-15.0.7/llvm/test/tools/yaml2obj/ELF/
H A D	mips-abi-flags.yaml	`8 # CHECK-NEXT: ISA: MIPS64r5 9 # CHECK-NEXT: ISA Extension: Cavium Networks Octeon3 (0x13) 36 ISA: MIPS64`
/llvm-project-15.0.7/llvm/test/tools/obj2yaml/ELF/
H A D	mips-abi-flags.yaml	`10 # CHECK-NEXT: ISA: MIPS64 31 ISA: MIPS64 56 # MIPS-NEXT: ISA: 0x0`

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