INT1 (reference) in projects: llvm-project-15.0.7

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Searched refs:INT1 (Results 1 – 25 of 28) sorted by relevance

/llvm-project-15.0.7/clang/test/Sema/
H A D	attr-deprecated-message.c	4 typedef int INT1 __attribute__((deprecated("Please avoid INT1"))); // expected-note 3 {{'INT1' has … typedef 6 typedef INT1 INT2 __attribute__ ((__deprecated__("Please avoid INT2"))); 8 typedef INT1 INT1a; // expected-warning {{'INT1' is deprecated: Please avoid INT1}} 10 typedef INT1 INT1b __attribute__ ((deprecated("Please avoid INT1b"))); 12 INT1 should_be_unavailable; // expected-warning {{'INT1' is deprecated: Please avoid INT1}} 15 INT1 f1(void) __attribute__ ((deprecated("Please avoid f1"))); // expected-note {{'f1' has been exp… 16 INT1 f2(void); // expected-warning {{'INT1' is deprecated: Please avoid INT1}}
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A D	legalize-fcos.mir	22 ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32) 31 ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32) 59 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64) 68 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64) 97 ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) 109 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 337 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INT1]](s16) 422 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 535 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INT1]](s16) 597 ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32) [all …]
H A D	legalize-fsin.mir	22 ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32) 31 ; VI-NEXT: $vgpr0 = COPY [[INT1]](s32) 59 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64) 68 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[INT1]](s64) 97 ; SI-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) 109 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 337 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INT1]](s16) 422 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 535 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INT1]](s16) 597 ; SI-NEXT: $vgpr0 = COPY [[INT1]](s32) [all …]
H A D	irtranslator-amdgpu_ps.ll	`71 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1… 72 ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) 88 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1… 89 ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) 104 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COP… 105 ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32)`
H A D	legalize-fpow.mir	54 …; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]… 55 ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] 69 …; GFX9-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]… 70 ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] 96 …; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG2_1]… 97 ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] 115 ; GFX9-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] 232 ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = G_FEXP2 [[INT1]] 264 ; GFX9-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) 306 ; GFX6-NEXT: [[FEXP2_1:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT1]] [all …]
H A D	regbankselect-amdgcn.div.scale.mir	`19 …; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32), [[INT1:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.am… 38 …; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32), [[INT1:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.am… 57 …; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32), [[INT1:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.am… 75 …; CHECK-NEXT: [[INT:%[0-9]+]]:vgpr(s32), [[INT1:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.am…`
H A D	irtranslator-metadata.ll	`10 …; CHECK: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.reloc.constant), <0x{{[0-9… 11 ; CHECK: [[SUM:%[0-9]+]]:_(s32) = G_ADD [[INT0]], [[INT1]]`
H A D	irtranslator-struct-return-intrinsics.ll	`15 …; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32), [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC intrinsic(@llvm.amdgc… 16 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[INT1]](s1)`
H A D	legalize-fdiv.mir	60 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 75 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 101 ; GFX10-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 1253 ; GFX9-UNSAFE-NEXT: [[FMA7:%[0-9]+]]:_(s64) = G_FMA [[FMA6]], [[INT1]], [[INT1]] 1384 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INT1]](s16) 1416 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 1593 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 1636 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) 1873 ; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[INT1]](s16) 2085 ; VI-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT1]](s16) [all …]
H A D	legalize-sitofp.mir	135 …; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), [[SITOFP]](s32),… 136 ; GFX6-NEXT: $vgpr0 = COPY [[INT1]](s32) 157 …; GFX8-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), [[SITOFP]](s32),… 158 ; GFX8-NEXT: $vgpr0 = COPY [[INT1]](s32) 479 …; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), [[SITOFP]](s32),… 480 ; GFX6-NEXT: $vgpr0 = COPY [[INT1]](s32) 503 ; GFX8-NEXT: $vgpr0 = COPY [[INT1]](s32) 537 ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) 561 ; GFX8-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) 598 ; GFX6-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) [all …]
H A D	irtranslator-atomicrmw.ll	`38 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), … 39 ; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3`
H A D	regbankselect-amdgcn.else.64.mir	`15 …; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1), [[INT1:%[0-9]+]]:sgpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS int…`
H A D	regbankselect-amdgcn.else.32.mir	`18 …; CHECK-NEXT: [[INT:%[0-9]+]]:vcc(s1), [[INT1:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_W_SIDE_EFFECTS int…`
H A D	irtranslator-amdgpu_vs.ll	`87 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COP… 88 ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32)`
H A D	combine-shift-imm-chain-illegal-types.mir	`227 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]]… 228 ; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32) 266 …; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]]… 267 ; CHECK-NEXT: $vgpr1 = COPY [[INT1]](s32)`
H A D	legalize-fptoui.mir	219 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64) 221 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]] 283 … ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64) 285 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]] 346 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64) 348 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
H A D	legalize-fptosi.mir	219 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64) 221 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]] 283 … ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64) 285 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = nnan G_FMINNUM_IEEE [[INT1]], [[C10]] 346 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s64) 348 ; SI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C10]]
H A D	legalize-uitofp.mir	`557 …; GFX6-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), [[UITOFP1]](s32)… 558 ; GFX6-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32) 593 …; GFX8-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), [[UITOFP1]](s32)… 594 ; GFX8-NEXT: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT1]](s32)`
H A D	legalize-intrinsic-trunc.mir	`311 …; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](s32), [[C]]… 312 ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]`
H A D	legalize-fceil.mir	`325 …; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[UV5]](s32), [[C]]… 326 ; SI-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]`
H A D	legalize-ffloor.mir	`279 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[UV1]](s64) 280 ; SI-NEXT: [[FMINNUM_IEEE1:%[0-9]+]]:_(s64) = G_FMINNUM_IEEE [[INT1]], [[C]]`
/llvm-project-15.0.7/clang/test/SemaObjC/
H A D	interface-1.m	`19 @interface INT1 interface 24 …INT1 b[3]; // expected-error {{array of interface 'INT1' is invalid (probably should be a… 25 INT1 *c = &b[0];`
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A D	legalize-ctpop.mir	247 …; CHECK: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT]]… 248 ; CHECK: $q0 = COPY [[INT1]](<4 x s32>) 269 …; CHECK: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT]]… 270 …INT2:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT1]](<4 x s32>) 313 …; CHECK: [[INT1:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT]]… 314 ; CHECK: $d0 = COPY [[INT1]](<2 x s32>)
/llvm-project-15.0.7/llvm/test/DebugInfo/COFF/
H A D	int8-char-type.ll	`4 ; with the T_[U]INT1 types. Non-C language frontends are likely use the normal`
/llvm-project-15.0.7/lldb/test/Shell/SymbolFile/DWARF/x86/
H A D	dwp.s	`8 # CHECK: (INT1) A = 1`

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