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/llvm-project-15.0.7/flang/include/flang/Common/
H A Dbit-population-count.h22 template <typename INT,
23 std::enable_if_t<(sizeof(INT) > 4 && sizeof(INT) <= 8), int> = 0>
24 inline constexpr int BitPopulationCount(INT x) { in BitPopulationCount()
40 template <typename INT,
41 std::enable_if_t<(sizeof(INT) > 2 && sizeof(INT) <= 4), int> = 0>
42 inline constexpr int BitPopulationCount(INT x) { in BitPopulationCount()
56 template <typename INT, std::enable_if_t<sizeof(INT) == 2, int> = 0>
57 inline constexpr int BitPopulationCount(INT x) { in BitPopulationCount()
69 template <typename INT, std::enable_if_t<sizeof(INT) == 1, int> = 0>
80 template <typename INT> inline constexpr bool Parity(INT x) { in Parity()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/function/
H A Dalloca-load-store.ll9 ; CHECK: [[INT:%.+]] = OpTypeInt 32
12 ; CHECK-DAG: [[FN1:%.+]] = OpTypeFunction [[INT]] [[INT]]
13 ; CHECK-DAG: [[FN2:%.+]] = OpTypeFunction [[INT]] [[INT]] [[GLOBAL_PTR]]
22 ; CHECK: [[BAR]] = OpFunction [[INT]] None [[FN1]]
23 ; CHECK: [[A:%.+]] = OpFunctionParameter [[INT]]
27 ; CHECK: [[B:%.+]] = OpLoad [[INT]] [[P]]
39 ; CHECK: [[FOO]] = OpFunction [[INT]] None [[FN1]]
40 ; CHECK: [[A:%.+]] = OpFunctionParameter [[INT]]
44 ; CHECK: [[B:%.+]] = OpLoad [[INT]] [[P]] Volatile
57 ; CHECK: [[A:%.+]] = OpFunctionParameter [[INT]]
[all …]
H A Didentity-function.ll8 ; CHECK: [[INT:%.+]] = OpTypeInt 32
9 ; CHECK: [[FN:%.+]] = OpTypeFunction [[INT]] [[INT]]
11 ; CHECK: [[IDENTITY]] = OpFunction [[INT]] None [[FN]]
12 ; CHECK-NEXT: [[VALUE]] = OpFunctionParameter [[INT]]
/llvm-project-15.0.7/llvm/test/CodeGen/SPIRV/constant/
H A Dglobal-constants.ll22 ; CHECK: [[INT:%.+]] = OpTypeInt 32
24 ; CHECK-DAG: [[PTR_TO_INT_AS1:%.+]] = OpTypePointer CrossWorkgroup [[INT]]
25 ; CHECK-DAG: [[PTR_TO_INT_AS2:%.+]] = OpTypePointer UniformConstant [[INT]]
26 ; CHECK-DAG: [[PTR_TO_INT_AS3:%.+]] = OpTypePointer Workgroup [[INT]]
28 ; CHECK-DAG: [[CST_AS1:%.+]] = OpConstant [[INT]] 1
29 ; CHECK-DAG: [[CST_AS2:%.+]] = OpConstant [[INT]] 2
30 ; CHECK-DAG: [[CST_AS3:%.+]] = OpConstant [[INT]] 3
36 ; CHECK: OpLoad [[INT]] [[GV1]]
37 ; CHECK: OpLoad [[INT]] [[GV2]]
38 ; CHECK: OpLoad [[INT]] [[GV3]]
H A Dlocal-null-constants.ll18 ; CHECK: [[INT:%.+]] = OpTypeInt 32
20 ; CHECK-DAG: [[PTR_AS1:%.+]] = OpTypePointer CrossWorkgroup [[INT]]
23 ; CHECK-DAG: [[PTR_AS2:%.+]] = OpTypePointer UniformConstant [[INT]]
26 ; CHECK-DAG: [[PTR_AS3:%.+]] = OpTypePointer Workgroup [[INT]]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpropagate-attributes-clone.ll22 ; OPT-INT: tail call void @foo4()
23 ; OPT-INT: tail call fastcc void @foo3.2()
24 ; OPT-INT: tail call fastcc void @foo2.3()
27 ; OPT-INT: tail call fastcc void @0()
31 ; OPT-INT: tail call fastcc void @foo1()
49 ; OPT-INT: tail call void @foo4()
50 ; OPT-INT: tail call fastcc void @foo3()
51 ; OPT-INT: tail call fastcc void @foo2()
52 ; OPT-INT: tail call fastcc void @foo2()
53 ; OPT-INT: tail call fastcc void @foo1()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-amdgcn.mfma.gfx90a.mir19 …; FAST-NEXT: [[INT:%[0-9]+]]:agpr(<32 x s32>) = G_INTRINSIC intrinsic(@llvm.amdgcn.mfma.f32.32x32x…
51 …_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[INT]](<16 x s32>)
59 …_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[INT]](<16 x s32>)
82 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
90 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
144 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
152 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
175 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INT]](<8 x s32>)
183 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 = COPY [[INT]](<8 x s32>)
206 ; FAST-NEXT: $vgpr0_vgpr1 = COPY [[INT]](<2 x s32>)
[all …]
H A Dregbankselect-amdgcn.mfma.gfx940.mir20 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
28 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
51 …_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = COPY [[INT]](<16 x s32>)
82 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
90 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
145 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
154 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
213 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
222 ; GREEDY-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
281 ; FAST-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
[all …]
H A Dregbankselect-amdgcn.mfma.mir118 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
144 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
216 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
242 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
363 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
389 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
461 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
487 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
608 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
634 ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[INT]](<4 x s32>)
[all …]
H A Dlegalize-amdgcn.rsq.clamp.mir20 …; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), […
21 ; SI-NEXT: $vgpr0 = COPY [[INT]](s32)
26 …; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]…
28 ; VI-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]]
52 …; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), […
53 ; SI-NEXT: $vgpr0 = COPY [[INT]](s32)
58 …; VI-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]…
60 ; VI-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]
H A Dlegalize-fcos.mir20 ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
21 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
30 ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s32)
39 ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
58 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), [[INT]](s64)
76 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
119 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
357 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
444 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
570 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
[all …]
H A Dlegalize-fsin.mir20 ; SI-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), [[FMUL]](s32)
21 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
30 ; VI-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s32)
39 ; GFX9-NEXT: $vgpr0 = COPY [[INT]](s32)
58 ; SI-NEXT: [[INT1:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[INT]](s64)
76 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[INT]](s64)
119 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
357 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
444 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
570 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[INT]](s16)
[all …]
H A Dlegalize-fpow.mir20 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
29 ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
52 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
67 ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
94 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
112 ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
140 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]]
149 ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan nsz G_FEXP2 [[INT]]
174 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = G_FEXP2 [[INT]]
189 ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
[all …]
H A Dregbankselect-amdgcn.ballot.i64.mir18 …; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[COPY1]](s1)
19 ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s64)
39 …; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[COPY1]](s1)
40 ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s64)
60 … ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), [[ICMP]](s1)
61 ; CHECK-NEXT: S_ENDPGM 0, implicit [[INT]](s64)
H A Dlegalize-fpowi.mir22 …; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG…
23 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]]
37 …; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FPEX…
38 ; GFX9-NEXT: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[INT]](s32)
63 …; GFX6-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG…
64 ; GFX6-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]]
73 …; GFX9-NEXT: [[INT:%[0-9]+]]:_(s32) = nnan G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[FLOG…
74 ; GFX9-NEXT: [[FEXP2_:%[0-9]+]]:_(s32) = nnan G_FEXP2 [[INT]]
H A Dlegalize-fdiv.mir35 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
134 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
153 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
237 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
258 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
523 ; GFX9-UNSAFE-NEXT: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FMA]], [[INT]], [[INT]]
1244 ; GFX9-UNSAFE-NEXT: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FMA]], [[INT]], [[INT]]
2285 ; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[INT]](s32)
2379 ; GFX9-UNSAFE-NEXT: $vgpr0 = COPY [[INT]](s32)
2487 ; GFX9-UNSAFE-NEXT: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FMA]], [[INT]], [[INT]]
[all …]
/llvm-project-15.0.7/llvm/test/DebugInfo/Generic/
H A Dmultiline.ll3 ; RUN: llc -filetype=obj -O0 < %s | llvm-dwarfdump -debug-line - | FileCheck %s --check-prefix=INT
32 ; INT: {{^}}Address
33 ; INT: -----
34 ; INT-NEXT: 2 0 1 0 0 is_stmt{{$}}
35 ; INT-NEXT: 3 3 1 0 0 is_stmt prologue_end{{$}}
36 ; INT-NEXT: 3 9 1 0 0 {{$}}
37 ; INT-NEXT: 3 15 1 0 0 {{$}}
38 ; INT-NEXT: 4 3 1 0 0 is_stmt{{$}}
39 ; INT-NEXT: 4 9 1 0 0 {{$}}
40 ; INT-NEXT: 4 15 1 0 0 {{$}}
[all …]
/llvm-project-15.0.7/flang/lib/Evaluate/
H A Dint-power.h18 template <typename REAL, typename INT>
20 const INT &power,
32 INT absPower{power.ABS().value};
34 int nbits{INT::bits - absPower.LEADZ()};
52 template <typename REAL, typename INT>
53 ValueWithRealFlags<REAL> IntPower(const REAL &base, const INT &power,
55 REAL one{REAL::FromInteger(INT{1}).value};
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dargs-09.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT
20 ; CHECK-INT-LABEL: foo:
21 ; CHECK-INT-DAG: lghi %r2, 1
22 ; CHECK-INT-DAG: lghi %r3, 2
23 ; CHECK-INT-DAG: lghi %r4, 3
24 ; CHECK-INT-DAG: lghi %r5, 4
25 ; CHECK-INT-DAG: la %r6, {{200|216}}(%r15)
26 ; CHECK-INT: brasl %r14, bar@PLT
H A Dargs-01.ll4 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT
23 ; CHECK-INT-LABEL: foo:
24 ; CHECK-INT-DAG: lhi %r2, 1
25 ; CHECK-INT-DAG: lhi %r3, 2
26 ; CHECK-INT-DAG: lhi %r4, 3
27 ; CHECK-INT-DAG: lghi %r5, 4
28 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
29 ; CHECK-INT: brasl %r14, bar@PLT
H A Dargs-03.ll4 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT
24 ; CHECK-INT-LABEL: foo:
25 ; CHECK-INT-DAG: lghi %r2, 255
26 ; CHECK-INT-DAG: llill %r3, 65534
27 ; CHECK-INT-DAG: llilf %r4, 4294967293
28 ; CHECK-INT-DAG: lghi %r5, -4
29 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
30 ; CHECK-INT: brasl %r14, bar@PLT
H A Dargs-02.ll4 ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT
24 ; CHECK-INT-LABEL: foo:
25 ; CHECK-INT-DAG: lghi %r2, -1
26 ; CHECK-INT-DAG: lghi %r3, -2
27 ; CHECK-INT-DAG: lghi %r4, -3
28 ; CHECK-INT-DAG: lghi %r5, -4
29 ; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
30 ; CHECK-INT: brasl %r14, bar@PLT
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-ctpop.mir72 …; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x…
73 ; CHECK: %ctpop:_(s64) = G_ZEXT [[INT]](s32)
93 …; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<16 …
95 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[INT]](s32), [[C]](s32)
121 …; CHECK: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x…
122 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
149 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
176 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
202 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
226 ; CHECK: $q0 = COPY [[INT]](<8 x s16>)
[all …]
/llvm-project-15.0.7/flang/unittests/Evaluate/
H A Dinteger.cpp16 static_cast<int>(sizeof(typename INT::Part)), INT::littleEndian); in exhaustiveTesting()
18 MATCH(BITS, INT::bits)(desc); in exhaustiveTesting()
20 INT zero; in exhaustiveTesting()
27 INT a{x}; in exhaustiveTesting()
29 INT copy{a}; in exhaustiveTesting()
37 auto readcheck{INT::Read(p)}; in exhaustiveTesting()
43 readcheck = INT::Read(p, 16); in exhaustiveTesting()
49 readcheck = INT::Read(p); in exhaustiveTesting()
55 readcheck = INT::Read(p, 16); in exhaustiveTesting()
59 INT t{a.NOT()}; in exhaustiveTesting()
[all …]
/llvm-project-15.0.7/flang/include/flang/Evaluate/
H A Dreal.h139 template <typename INT> constexpr INT EXPONENT() const { in EXPONENT()
141 return INT::HUGE(); in EXPONENT()
177 template <typename INT>
178 ValueWithRealFlags<Real> SCALE(const INT &by,
183 } else if (by > INT{maxExponent}) {
185 } else if (by < INT{-exponentBias}) {
224 template <typename INT>
228 INT absN{n};
258 template <typename INT>
259 constexpr ValueWithRealFlags<INT> ToInteger(
[all …]

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