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/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Dmachine-csr-names.s35 # CHECK-INST-ALIAS: csrr t1, marchid
49 # CHECK-INST-ALIAS: csrr t1, mimpid
53 # CHECK-INST-ALIAS: csrr t2, mimpid
108 # CHECK-INST-ALIAS: csrr t1, misa
112 # CHECK-INST-ALIAS: csrr t2, misa
150 # CHECK-INST: csrrs t1, mie, zero
152 # CHECK-INST-ALIAS: csrr t1, mie
154 # CHECK-INST: csrrs t2, mie, zero
156 # CHECK-INST-ALIAS: csrr t2, mie
250 # CHECK-INST-ALIAS: csrr t1, mip
[all …]
H A Drv32-machine-csr-names.s13 # CHECK-INST: csrrs t1, mstatush, zero
15 # CHECK-INST-ALIAS: csrr t1, mstatush
17 # CHECK-INST: csrrs t2, mstatush, zero
19 # CHECK-INST-ALIAS: csrr t2, mstatush
31 # CHECK-INST: csrrs t1, menvcfgh, zero
33 # CHECK-INST-ALIAS: csrr t1, menvcfgh
37 # CHECK-INST-ALIAS: csrr t2, menvcfgh
47 # CHECK-INST-ALIAS: csrr t1, mseccfgh
65 # CHECK-INST-ALIAS: csrr t1, pmpcfg1
69 # CHECK-INST-ALIAS: csrr t2, pmpcfg1
[all …]
H A Duser-csr-names.s32 # CHECK-INST: csrrs t1, uie, zero
34 # CHECK-INST-ALIAS: csrr t1, uie
36 # CHECK-INST: csrrs t2, uie, zero
38 # CHECK-INST-ALIAS: csrr t2, uie
48 # CHECK-INST-ALIAS: csrr t1, utvec
122 # CHECK-INST-ALIAS: csrr t1, uip
126 # CHECK-INST-ALIAS: csrr t2, uip
145 # CHECK-INST-ALIAS: rdcycle t1
149 # CHECK-INST-ALIAS: rdcycle t2
159 # CHECK-INST-ALIAS: rdtime t1
[all …]
H A Drv32-user-csr-names.s13 # CHECK-INST: csrrs t1, cycleh, zero
15 # CHECK-INST-ALIAS: rdcycleh t1
17 # CHECK-INST: csrrs t2, cycleh, zero
19 # CHECK-INST-ALIAS: rdcycleh t2
27 # CHECK-INST: csrrs t1, timeh, zero
29 # CHECK-INST-ALIAS: rdtimeh t1
31 # CHECK-INST: csrrs t2, timeh, zero
33 # CHECK-INST-ALIAS: rdtimeh t2
41 # CHECK-INST: csrrs t1, instreth, zero
43 # CHECK-INST-ALIAS: rdinstreth t1
[all …]
H A Drv64-machine-csr-names.s16 # CHECK-INST: csrrs t2, 929, zero
18 # CHECK-INST-ALIAS: csrr t2, 929
23 # CHECK-INST: csrrs t2, 931, zero
25 # CHECK-INST-ALIAS: csrr t2, 931
33 # CHECK-INST: csrrs t2, 2944, zero
35 # CHECK-INST-ALIAS: csrr t2, 2944
40 # CHECK-INST: csrrs t2, 2946, zero
42 # CHECK-INST-ALIAS: csrr t2, 2946
49 # CHECK-INST-ALIAS: csrr t2, 2947
56 # CHECK-INST-ALIAS: csrr t2, 2948
[all …]
H A Drv64-user-csr-names.s16 # CHECK-INST: csrrs t2, 3200, zero
18 # CHECK-INST-ALIAS: csrr t2, 3200
23 # CHECK-INST: csrrs t2, 3201, zero
25 # CHECK-INST-ALIAS: csrr t2, 3201
30 # CHECK-INST: csrrs t2, 3202, zero
32 # CHECK-INST-ALIAS: csrr t2, 3202
37 # CHECK-INST: csrrs t2, 3203, zero
39 # CHECK-INST-ALIAS: csrr t2, 3203
46 # CHECK-INST-ALIAS: csrr t2, 3204
53 # CHECK-INST-ALIAS: csrr t2, 3205
[all …]
H A Dhypervisor-csr-names.s19 # CHECK-INST: csrrs t1, hstatus, zero
21 # CHECK-INST-ALIAS: csrr t1, hstatus
25 # CHECK-INST-ALIAS: csrr t2, hstatus
61 # CHECK-INST: csrrs t1, hie, zero
63 # CHECK-INST-ALIAS: csrr t1, hie
65 # CHECK-INST: csrrs t2, hie, zero
67 # CHECK-INST-ALIAS: csrr t2, hie
121 # CHECK-INST: csrrs t1, hip, zero
123 # CHECK-INST-ALIAS: csrr t1, hip
125 # CHECK-INST: csrrs t2, hip, zero
[all …]
H A Dsupervisor-csr-names.s19 # CHECK-INST: csrrs t1, sstatus, zero
21 # CHECK-INST-ALIAS: csrr t1, sstatus
25 # CHECK-INST-ALIAS: csrr t2, sstatus
61 # CHECK-INST: csrrs t1, sie, zero
63 # CHECK-INST-ALIAS: csrr t1, sie
65 # CHECK-INST: csrrs t2, sie, zero
67 # CHECK-INST-ALIAS: csrr t2, sie
77 # CHECK-INST-ALIAS: csrr t1, stvec
81 # CHECK-INST-ALIAS: csrr t2, stvec
199 # CHECK-INST-ALIAS: csrr t1, sip
[all …]
H A Drvv-user-csr-names.s21 # CHECK-INST-ALIAS: csrr t1, vstart
35 # CHECK-INST-ALIAS: csrr t1, vxsat
39 # CHECK-INST-ALIAS: csrr t2, vxsat
49 # CHECK-INST-ALIAS: csrr t1, vxrm
53 # CHECK-INST-ALIAS: csrr t2, vxrm
63 # CHECK-INST-ALIAS: csrr t1, vcsr
67 # CHECK-INST-ALIAS: csrr t2, vcsr
75 # CHECK-INST: csrrs t1, vl, zero
77 # CHECK-INST-ALIAS: csrr t1, vl
79 # CHECK-INST: csrrs t2, vl, zero
[all …]
H A Dpriv-valid.s12 # CHECK-INST: uret
16 # CHECK-INST: sret
20 # CHECK-INST: mret
24 # CHECK-INST: wfi
44 # CHECK-INST: sfence.w.inval
48 # CHECK-INST: sfence.inval.ir
84 # CHECK-INST: hlv.b a0, (a1)
92 # CHECK-INST: hlv.h a1, (a2)
104 # CHECK-INST: hlv.w a2, (a2)
112 # CHECK-INST: hsv.b a0, (a1)
[all …]
H A Drv32-hypervisor-csr-names.s13 # CHECK-INST: csrrs t1, henvcfgh, zero
15 # CHECK-INST-ALIAS: csrr t1, henvcfgh
17 # CHECK-INST: csrrs t2, henvcfgh, zero
19 # CHECK-INST-ALIAS: csrr t2, henvcfgh
31 # CHECK-INST: csrrs t1, htimedeltah, zero
33 # CHECK-INST-ALIAS: csrr t1, htimedeltah
37 # CHECK-INST-ALIAS: csrr t2, htimedeltah
49 # CHECK-INST: csrrs t1, vstimecmph, zero
51 # CHECK-INST-ALIAS: csrr t1, vstimecmph
55 # CHECK-INST-ALIAS: csrr t2, vstimecmph
[all …]
H A Drvf-user-csr-names.s25 # CHECK-INST: csrrs t1, fflags, zero
27 # CHECK-INST-ALIAS: frflags t1
32 # CHECK-INST-ALIAS: frflags t2
41 # CHECK-INST: csrrs t1, frm, zero
43 # CHECK-INST-ALIAS: frrm t1
46 # CHECK-INST: csrrs t2, frm, zero
48 # CHECK-INST-ALIAS: frrm t2
57 # CHECK-INST: csrrs t1, fcsr, zero
59 # CHECK-INST-ALIAS: frcsr t1
62 # CHECK-INST: csrrs t2, fcsr, zero
[all …]
H A Doption-pushpop.s22 # CHECK-INST: call foo
33 # CHECK-INST: .option push
37 # CHECK-INST: call bar
43 # CHECK-INST: .option push
46 # CHECK-INST: .option rvc
53 # CHECK-INST: .option pop
59 # CHECK-INST: call bar
65 # CHECK-INST: .option pop
66 # CHECK-INST: call baz
80 # CHECK-INST: .option pic
[all …]
H A Drvf-aliases-valid.s26 # CHECK-INST: flw ft0, 0(a0)
29 # CHECK-INST: fsw ft0, 0(a0)
43 # CHECK-INST: flt.s tp, ft6, ft5
46 # CHECK-INST: fle.s t2, fs1, fs0
55 # CHECK-INST: csrrw t1, fcsr, t2
67 # CHECK-INST: csrrw t5, fcsr, t6
77 # CHECK-INST: csrrw t5, frm, t4
106 # CHECK-INST: fmv.x.w a2, fs7
109 # CHECK-INST: fmv.w.x ft1, a6
113 # CHECK-INST: flw ft0, 0(a0)
[all …]
/llvm-project-15.0.7/llvm/test/MC/MSP430/
H A Dopcode.s8 mov.b r7, r8 ; CHECK-INST: mov.b r7, r8
10 add.b r7, r8 ; CHECK-INST: add.b r7, r8
136 dint ; CHECK-INST: dint
138 eint ; CHECK-INST: eint
140 nop ; CHECK-INST: nop
148 clrc ; CHECK-INST: clrc
150 clrn ; CHECK-INST: clrn
152 clrz ; CHECK-INST: clrz
156 setc ; CHECK-INST: setc
158 setn ; CHECK-INST: setn
[all …]
/llvm-project-15.0.7/llvm/test/MC/AVR/
H A Dinst-family-set-clr-flag.s108 ; CHECK-INST: sec
109 ; CHECK-INST: sec
110 ; CHECK-INST: sez
111 ; CHECK-INST: sez
112 ; CHECK-INST: sen
113 ; CHECK-INST: sen
114 ; CHECK-INST: sev
115 ; CHECK-INST: sev
116 ; CHECK-INST: ses
117 ; CHECK-INST: ses
[all …]
H A Dinst-st.s75 ; INST: st X, r10
76 ; INST: st X, r17
82 ; INST: st X+, r10
83 ; INST: st X+, r17
84 ; INST: st Y+, r30
85 ; INST: st Y+, r19
86 ; INST: st Z+, r10
87 ; INST: st Z+, r2
89 ; INST: st -X, r10
90 ; INST: st -X, r17
[all …]
H A Dinst-ld.s77 ; INST: ld r10, X
78 ; INST: ld r17, X
84 ; INST: ld r10, X+
85 ; INST: ld r17, X+
86 ; INST: ld r30, Y+
87 ; INST: ld r19, Y+
88 ; INST: ld r10, Z+
89 ; INST: ld r2, Z+
91 ; INST: ld r10, -X
92 ; INST: ld r17, -X
[all …]
/llvm-project-15.0.7/llvm/test/MC/VE/
H A DSMIR.s6 # CHECK-INST: smir %s11, %usrcc
10 # CHECK-INST: smir %s11, %usrcc
14 # CHECK-INST: smir %s11, %psw
18 # CHECK-INST: smir %s11, %psw
22 # CHECK-INST: smir %s11, %sar
26 # CHECK-INST: smir %s11, %sar
30 # CHECK-INST: smir %s11, %pmmr
34 # CHECK-INST: smir %s11, %pmmr
38 # CHECK-INST: smir %s11, %pmcr0
42 # CHECK-INST: smir %s11, %pmcr0
[all …]
H A DVST.s6 # CHECK-INST: vst %v11, 23, %s12
10 # CHECK-INST: vst.nc %vix, 63, %s22
14 # CHECK-INST: vst.ot %v63, -64, %s63
18 # CHECK-INST: vst.nc.ot %v12, %s12, 0
22 # CHECK-INST: vst %v11, 23, %s12
38 # CHECK-INST: vstu %v11, 23, %s12
42 # CHECK-INST: vstu.nc %vix, 63, %s22
54 # CHECK-INST: vstu %v11, 23, %s12
70 # CHECK-INST: vstl %v11, 23, %s12
86 # CHECK-INST: vstl %v11, 23, %s12
[all …]
H A DVFMF.s6 # CHECK-INST: vfmk.d.at %vm11
10 # CHECK-INST: vfmk.d.at %vm11
14 # CHECK-INST: vfmk.d.af %vm1, %vm15
18 # CHECK-INST: vfmk.d.gt %vm12, %v22
26 # CHECK-INST: vfmk.d.ne %vm11, %v32
34 # CHECK-INST: vfmk.d.ge %vm12, %v22
42 # CHECK-INST: vfmk.d.num %vm11, %v45
74 # CHECK-INST: pvfmk.s.up.at %vm11
78 # CHECK-INST: pvfmk.s.up.at %vm11
142 # CHECK-INST: pvfmk.s.up.at %vm11
[all …]
H A DBC.s6 # CHECK-INST: b.l 8199
10 # CHECK-INST: b.l.t 20(, %s11)
14 # CHECK-INST: baf.l.nt -1(, %s11)
18 # CHECK-INST: b.w.t 20(, %s11)
22 # CHECK-INST: baf.d.nt -1(, %s11)
26 # CHECK-INST: b.s.t 20(, %s11)
34 # CHECK-INST: bgt.l.t %s20, 8192
42 # CHECK-INST: blt.w.t %s20, 8192
50 # CHECK-INST: bne.l.t %s20, 8192
58 # CHECK-INST: beq.w.t %s20, 8192
[all …]
H A DBCR.s6 # CHECK-INST: br.l 8199
10 # CHECK-INST: br.w.t -224
14 # CHECK-INST: braf.d.nt 224
18 # CHECK-INST: brgt.s 23, %s20, 224
22 # CHECK-INST: brlt.l %s18, 0, -224
26 # CHECK-INST: brlt.l.t 23, %s20, -224
30 # CHECK-INST: brne.w.nt 23, %s20, 8192
34 # CHECK-INST: breq.d 23, %s20, -224
38 # CHECK-INST: breq.d %s20, 0, -224
42 # CHECK-INST: brge.s.t 23, %s20, 8192
[all …]
H A DVFMS.s6 # CHECK-INST: vfmk.w.at %vm11
10 # CHECK-INST: vfmk.w.at %vm1, %vm15
14 # CHECK-INST: vfmk.w.af %vm1, %vm15
18 # CHECK-INST: vfmk.w.gt %vm12, %v22
26 # CHECK-INST: vfmk.w.ne %vm11, %v32
34 # CHECK-INST: vfmk.w.ge %vm12, %v22
42 # CHECK-INST: vfmk.w.at %vm11
46 # CHECK-INST: vfmk.w.at %vm1, %vm15
50 # CHECK-INST: vfmk.w.af %vm1, %vm15
54 # CHECK-INST: vfmk.w.gt %vm12, %v22
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dzvlsseg.s13 # CHECK-INST: vlseg2e8.v v8, (a0), v0.t
19 # CHECK-INST: vlseg2e8.v v8, (a0)
31 # CHECK-INST: vlseg2e16.v v8, (a0)
43 # CHECK-INST: vlseg2e32.v v8, (a0)
55 # CHECK-INST: vlseg2e64.v v8, (a0)
67 # CHECK-INST: vlseg2e8ff.v v8, (a0)
79 # CHECK-INST: vlseg2e16ff.v v8, (a0)
91 # CHECK-INST: vlseg2e32ff.v v8, (a0)
259 # CHECK-INST: vlseg3e8.v v8, (a0)
271 # CHECK-INST: vlseg3e16.v v8, (a0)
[all …]

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