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Searched refs:INS2 (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dvector_insertelt_shuffle.ll7 ; CHECK-NEXT: [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, flo…
8 ; CHECK-NEXT: ret <4 x float> [[INS2]]
20 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A:%.*]], i64 1
21 ; CHECK-NEXT: ret <4 x float> [[INS2]]
31 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 2.000000e+00, i32 [[A:%.*…
32 ; CHECK-NEXT: ret <4 x float> [[INS2]]
43 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 5.000000e+00, i32 [[A:%.*…
44 ; CHECK-NEXT: [[INS5:%.*]] = shufflevector <4 x float> [[INS2]], <4 x float> <float poison, floa…
H A Dvector_insertelt_shuffle-inseltpoison.ll7 ; CHECK-NEXT: [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, flo…
8 ; CHECK-NEXT: ret <4 x float> [[INS2]]
20 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[TMP1]], float [[A:%.*]], i64 1
21 ; CHECK-NEXT: ret <4 x float> [[INS2]]
31 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 2.000000e+00, i32 [[A:%.*…
32 ; CHECK-NEXT: ret <4 x float> [[INS2]]
43 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float 5.000000e+00, i32 [[A:%.*…
44 ; CHECK-NEXT: [[INS5:%.*]] = shufflevector <4 x float> [[INS2]], <4 x float> <float poison, floa…
H A Dvec_gep_scalar_arg.ll7 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x i16*> undef, i16* [[T3]], i64 0
8 ; CHECK-NEXT: ret <4 x i16*> [[INS2]]
H A Dvec_gep_scalar_arg-inseltpoison.ll7 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x i16*> poison, i16* [[T3]], i64 0
8 ; CHECK-NEXT: ret <4 x i16*> [[INS2]]
H A Dinsert-const-shuf-inseltpoison.ll20 ; CHECK-NEXT: [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, flo…
21 ; CHECK-NEXT: ret <4 x float> [[INS2]]
H A Dinsert-const-shuf.ll20 ; CHECK-NEXT: [[INS2:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, flo…
21 ; CHECK-NEXT: ret <4 x float> [[INS2]]
H A Dbroadcast.ll166 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[V]], i64 2
167 ; CHECK-NEXT: [[INS3:%.*]] = insertelement <4 x float> [[INS2]], float [[V]], i64 3
H A Dbroadcast-inseltpoison.ll166 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[V]], i64 2
167 ; CHECK-NEXT: [[INS3:%.*]] = insertelement <4 x float> [[INS2]], float [[V]], i64 3
H A Dinsert-extract-shuffle-inseltpoison.ll248 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[EXT1]], i64 3
249 ; CHECK-NEXT: ret <4 x float> [[INS2]]
H A Dinsert-extract-shuffle.ll248 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x float> [[INS1]], float [[EXT1]], i64 3
249 ; CHECK-NEXT: ret <4 x float> [[INS2]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dinsert-shuffle.ll25 ; CHECK-NEXT: [[INS2:%.*]] = insertvalue { <2 x float>, <2 x float> } [[INS1]], <2 x float> [[TM…
26 ; CHECK-NEXT: ret { <2 x float>, <2 x float> } [[INS2]]
/llvm-project-15.0.7/llvm/test/Transforms/InterleavedAccess/AArch64/
H A Dsve-interleaved-accesses.ll70 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.v16i16(<vsca…
72 …aarch64.sve.st2.nxv8i16(<vscale x 8 x i16> [[INS1]], <vscale x 8 x i16> [[INS2]], <vscale x 8 x i1…
86 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v8i32(<vscal…
90 …aarch64.sve.st3.nxv4i32(<vscale x 4 x i32> [[INS1]], <vscale x 4 x i32> [[INS2]], <vscale x 4 x i3…
108 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscal…
197 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscal…
199 …aarch64.sve.st2.nxv2i64(<vscale x 2 x i64> [[INS1]], <vscale x 2 x i64> [[INS2]], <vscale x 2 x i1…
214 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscal…
235 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscal…
282 ; CHECK-NEXT: [[INS2:%.*]] = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v4i64(<vscal…
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dscalable-vector.ll121 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <vscale x 4 x i8> [[INS1]], i8 [[X3X3]], i32 1
122 ; CHECK-NEXT: [[INS3:%.*]] = insertelement <vscale x 4 x i8> [[INS2]], i8 [[Y1Y1]], i32 2
/llvm-project-15.0.7/compiler-rt/lib/fuzzer/tests/
H A DFuzzerUnittest.cpp180 uint8_t INS2[8] = {0x00, 0x11, 0xF3, 0x22, 0x33, 0x44, 0x55, 0x66}; in TestInsertByte() local
191 if (NewSize == 8 && !memcmp(INS2, T, 8)) FoundMask |= 1 << 2; in TestInsertByte()
216 uint8_t INS2[7] = {0x00, 0x11, 'a', 'a', 'a', 0x22, 0x33}; in TestInsertRepeatedBytes() local
231 if (NewSize == 7 && !memcmp(INS2, T, 7)) FoundMask |= 1 << 2; in TestInsertRepeatedBytes()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dsingle-value-blend-phis.ll167 ; CHECK-NEXT: [[INS2:%.+]] = insertelement <2 x i16> [[INS1]], i16 [[TMP9]], i32 1
171 ; CHECK-NEXT: store <2 x i16> [[INS2]], <2 x i16>* [[DST1_BC]], align 2
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dstrict-fadd.ll276 ; CHECK-UNORDERED: %[[INS2:.*]] = insertelement <4 x float> <float -0.000000e+00, float -0.000000e+…
279 ; CHECK-UNORDERED: %[[VEC_PHI2:.*]] = phi <4 x float> [ %[[INS2]], %vector.ph ], [ %[[VEC_FADD2:.*]…
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-demanded-vector-elts-inseltpoison.ll197 ; CHECK-NEXT: [[INS2:%.*]] = insertvalue { float, float, float } [[INS1]], float [[ELT2]], 2
198 ; CHECK-NEXT: ret { float, float, float } [[INS2]]
H A Damdgcn-demanded-vector-elts.ll197 ; CHECK-NEXT: [[INS2:%.*]] = insertvalue { float, float, float } [[INS1]], float [[ELT2]], 2
198 ; CHECK-NEXT: ret { float, float, float } [[INS2]]