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Searched refs:INS0 (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/CodeGenPrepare/AMDGPU/
H A Dbypass-slow-div-debug-info-inseltpoison.ll51 ; CHECK-NEXT: [[INS0:%.*]] = insertelement <2 x i64> poison, i64 [[TMP15]], i32 0
52 ; CHECK-NEXT: [[INS1:%.*]] = insertelement <2 x i64> [[INS0]], i64 [[TMP16]], i32 1
H A Dbypass-slow-div-debug-info.ll51 ; CHECK-NEXT: [[INS0:%.*]] = insertelement <2 x i64> undef, i64 [[TMP15]], i32 0
52 ; CHECK-NEXT: [[INS1:%.*]] = insertelement <2 x i64> [[INS0]], i64 [[TMP16]], i32 1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dindirect-addressing-si-pregfx9.ll15 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
H A Dindirect-addressing-si-gfx9.ll12 ; GCN-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62
H A Damdgpu-codegenprepare-fdiv.ll115 ; CHECK: %[[INS0:[0-9]+]] = insertelement <2 x float> undef, float %[[FDIV0]], i64 0
119 ; CHECK: %md.25ulp = insertelement <2 x float> %[[INS0]], float %[[FDIV1]], i64 1
/llvm-project-15.0.7/flang/test/Fir/
H A Dbox.fir30 …// CHECK: %[[INS0:.*]] = insertvalue {{.*}} { ptr undef, i64 4, i32 20180515, i8 0, i8 27, i8 0, i…
31 // CHECK: store {{.*}} %[[INS0]], {{.*}} %[[DESC]]
/llvm-project-15.0.7/compiler-rt/lib/fuzzer/tests/
H A DFuzzerUnittest.cpp178 uint8_t INS0[8] = {0xF1, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66}; in TestInsertByte() local
189 if (NewSize == 8 && !memcmp(INS0, T, 8)) FoundMask |= 1 << 0; in TestInsertByte()
214 uint8_t INS0[7] = {0x00, 0x11, 0x22, 0x33, 'a', 'a', 'a'}; in TestInsertRepeatedBytes() local
229 if (NewSize == 7 && !memcmp(INS0, T, 7)) FoundMask |= 1 << 0; in TestInsertRepeatedBytes()
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AMDGPU/
H A Damdgcn-demanded-vector-elts-inseltpoison.ll177 ; CHECK-NEXT: [[INS0:%.*]] = insertvalue { float, float } undef, float [[ELT0]], 0
178 ; CHECK-NEXT: [[INS1:%.*]] = insertvalue { float, float } [[INS0]], float [[ELT1]], 1
195 ; CHECK-NEXT: [[INS0:%.*]] = insertvalue { float, float, float } undef, float [[ELT0]], 0
196 ; CHECK-NEXT: [[INS1:%.*]] = insertvalue { float, float, float } [[INS0]], float [[ELT1]], 1
H A Damdgcn-demanded-vector-elts.ll177 ; CHECK-NEXT: [[INS0:%.*]] = insertvalue { float, float } undef, float [[ELT0]], 0
178 ; CHECK-NEXT: [[INS1:%.*]] = insertvalue { float, float } [[INS0]], float [[ELT1]], 1
195 ; CHECK-NEXT: [[INS0:%.*]] = insertvalue { float, float, float } undef, float [[ELT0]], 0
196 ; CHECK-NEXT: [[INS1:%.*]] = insertvalue { float, float, float } [[INS0]], float [[ELT1]], 1