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Searched refs:IAdd (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/mlir/test/Target/SPIRV/
H A Dconstant.mlir25 %3 = spv.IAdd %0, %1 : i32
26 %4 = spv.IAdd %2, %3 : i32
39 %3 = spv.IAdd %0, %1 : si32
40 %4 = spv.IAdd %2, %3 : si32
56 %3 = spv.IAdd %0, %1 : ui32
57 %4 = spv.IAdd %2, %3 : ui32
72 %4 = spv.IAdd %0, %1 : i64
73 %5 = spv.IAdd %2, %3 : i64
84 %2 = spv.IAdd %0, %1 : i16
107 %10 = spv.IAdd %0, %1: i8
[all …]
H A Dloop.mlir40 // CHECK-NEXT: spv.IAdd
41 %add = spv.IAdd %val1, %one : i32
95 // CHECK: %[[ADD:.*]] = spv.IAdd
96 %14 = spv.IAdd %9, %8 : i32
173 // CHECK-NEXT: spv.IAdd
174 %add = spv.IAdd %jval1, %one : i32
194 // CHECK-NEXT: spv.IAdd
195 %add = spv.IAdd %ival1, %one : i32
H A Dphi.mlir59 // CHECK-NEXT: %[[ADD:.*]] = spv.IAdd %[[ARG]], %[[ARG]] : i32
60 %0 = spv.IAdd %arg0, %arg0 : i32
215 // CHECK: %[[ADD1:.*]] = spv.IAdd
216 %48 = spv.IAdd %37, %35 : i32
224 // CHECK: %[[ADD2:.*]] = spv.IAdd %[[LP1_HDR_ARG]]
225 %36 = spv.IAdd %32, %31 : i32
261 %loop1_add = spv.IAdd %loop1_bb_arg, %cst4 : i32
277 %loop2_add = spv.IAdd %loop2_bb_arg, %cst4 : i32
H A Dspec-constant.mlir24 // CHECK: spv.IAdd %[[USE1]], %[[USE2]]
27 %1 = spv.IAdd %0, %0 : i32
39 // CHECK: spv.IAdd %[[ITM0]], %[[ITM1]]
44 %3 = spv.IAdd %1, %2 : i32
H A Darithmetic-ops.mlir40 // CHECK: {{%.*}} = spv.IAdd {{%.*}}, {{%.*}} : vector<4xi32>
41 %0 = spv.IAdd %arg0, %arg1 : vector<4xi32>
H A Ddebug.mlir98 %add = spv.IAdd %jval1, %one : i32
111 %add = spv.IAdd %ival1, %one : i32
H A Dcooperative-matrix-ops.mlir48 // CHECK: {{%.*}} = spv.IAdd {{%.*}}, {{%.*}} : !spv.coopmatrix<8x16xi32, Subgroup>
49 %r = spv.IAdd %a, %b : !spv.coopmatrix<8x16xi32, Subgroup>
H A Dfunction-call.mlir49 %1 = spv.IAdd %0, %one : i32
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/Transforms/
H A Dvce-deduction.mlir8 // spv.IAdd is available from v1.0.
16 %0 = spv.IAdd %val, %val: i32
47 %0 = spv.IAdd %val, %val: i32
73 %0 = spv.IAdd %val, %val: i32
119 %0 = spv.IAdd %val, %val : i8
143 %0 = spv.IAdd %val, %val : vector<16xi32>
177 %0 = spv.IAdd %val, %val: i32
193 %1 = spv.IAdd %0, %0 : i16
H A Dabi-load-store.mlir100 // CHECK: spv.IAdd [[ARG3]]
101 %36 = spv.IAdd %arg3, %2 : i32
102 // CHECK: spv.IAdd [[ARG4]]
103 %37 = spv.IAdd %arg4, %11 : i32
H A Dcanonicalize.mlir177 // spv.IAdd
184 %0 = spv.IAdd %arg0, %zero : i32
185 %1 = spv.IAdd %zero, %arg0 : i32
198 %0 = spv.IAdd %c5, %c5 : i32
199 %1 = spv.IAdd %cn8, %cn8 : i32
200 %2 = spv.IAdd %c5, %cn8 : i32
221 %0 = spv.IAdd %c1, %c3 : i32
222 %1 = spv.IAdd %c2, %c3 : i32
223 %2 = spv.IAdd %c4, %c5 : i32
224 %3 = spv.IAdd %c4, %c6 : i32
[all …]
/llvm-project-15.0.7/mlir/test/Conversion/TensorToSPIRV/
H A Dtensor-ops-to-spirv.mlir16 // CHECK: %[[ADD0:.+]] = spv.IAdd %[[C0]], %[[MUL0]] : i32
19 // CHECK: %[[ADD1:.+]] = spv.IAdd %[[ADD0]], %[[MUL1]] : i32
22 // CHECK: %[[ADD2:.+]] = spv.IAdd %[[ADD1]], %[[MUL2]] : i32
/llvm-project-15.0.7/mlir/test/Conversion/SCFToSPIRV/
H A Dfor.mlir25 // CHECK: %[[INDEX1:.*]] = spv.IAdd %[[OFFSET1]], %[[UPDATE1]] : i32
31 // CHECK: %[[INDEX2:.*]] = spv.IAdd %[[OFFSET2]], %[[UPDATE2]] : i32
33 // CHECK: %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
66 // CHECK-DAG: %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
/llvm-project-15.0.7/mlir/test/Conversion/GPUToSPIRV/
H A Dload-store.mlir58 // CHECK: %[[INDEX1:.*]] = spv.IAdd %[[ARG3]], %[[WORKGROUPIDX]]
60 // CHECK: %[[INDEX2:.*]] = spv.IAdd %[[ARG4]], %[[LOCALINVOCATIONIDX]]
66 // CHECK: %[[OFFSET1_1:.*]] = spv.IAdd %[[OFFSET1_0]], %[[UPDATE1_1]] : i32
69 // CHECK: %[[OFFSET1_2:.*]] = spv.IAdd %[[OFFSET1_1]], %[[UPDATE1_2]] : i32
/llvm-project-15.0.7/mlir/test/Conversion/SPIRVToLLVM/
H A Darithmetic-ops-to-llvm.mlir4 // spv.IAdd
10 %0 = spv.IAdd %arg0, %arg1 : i32
17 %0 = spv.IAdd %arg0, %arg1 : vector<4xi64>
H A Dfunc-ops-to-llvm.mlir59 %0 = spv.IAdd %arg0, %arg1 : vector<2xi64>
/llvm-project-15.0.7/mlir/lib/Conversion/LinalgToSPIRV/
H A DLinalgToSPIRV.cpp163 CREATE_GROUP_NON_UNIFORM_BIN_OP(IAdd, GroupNonUniformIAddOp); in matchAndRewrite()
192 switch (*binaryOpKind) { CREATE_ATOMIC_BIN_OP(IAdd, AtomicIAddOp); } in matchAndRewrite()
/llvm-project-15.0.7/mlir/test/Dialect/SPIRV/IR/
H A Darithmetic-ops.mlir118 // spv.IAdd
122 // CHECK: spv.IAdd
123 %0 = spv.IAdd %arg, %arg : i32
H A Davailability.mlir9 %0 = spv.IAdd %arg, %arg: i32
H A Dcooperative-matrix-ops.mlir55 // CHECK: {{%.*}} = spv.IAdd {{%.*}}, {{%.*}} : !spv.coopmatrix<8x16xi32, Subgroup>
56 %r = spv.IAdd %a, %b : !spv.coopmatrix<8x16xi32, Subgroup>
H A Dstructure-ops.mlir784 // CHECK: spv.SpecConstantOperation wraps "spv.IAdd"([[LHS]], [[RHS]]) : (i32, i32) -> i32
785 %2 = spv.SpecConstantOperation wraps "spv.IAdd"(%0, %1) : (i32, i32) -> i32
835 %2 = spv.SpecConstantOperation wraps "spv.IAdd"(%1, %1) : (i32, i32) -> i32
/llvm-project-15.0.7/mlir/test/Conversion/VectorToSPIRV/
H A Dvector-to-spirv.mlir242 // CHECK: %[[ADD0:.+]] = spv.IAdd %[[S0]], %[[S1]]
243 // CHECK: %[[ADD1:.+]] = spv.IAdd %[[ADD0]], %[[S2]]
244 // CHECK: %[[ADD2:.+]] = spv.IAdd %[[ADD1]], %[[S3]]
/llvm-project-15.0.7/mlir/test/Conversion/MemRefToSPIRV/
H A Dmemref-to-spirv.mlir77 // CHECK: %[[ADD:.+]] = spv.IAdd %[[ZERO_1]], %[[MUL]] : i32
98 // CHECK: %[[ADD:.+]] = spv.IAdd %[[ZERO_1]], %[[MUL]] : i32
174 // CHECK: %[[FLAT_IDX:.+]] = spv.IAdd %[[OFFSET]], %[[UPDATE]] : i32
271 // CHECK: %[[FLAT_IDX:.+]] = spv.IAdd %[[OFFSET]], %[[UPDATE]] : i32
/llvm-project-15.0.7/mlir/include/mlir/Dialect/SPIRV/IR/
H A DSPIRVArithmeticOps.td273 def SPV_IAddOp : SPV_ArithmeticBinaryOp<"IAdd",
295 iadd-op ::= ssa-id `=` `spv.IAdd` ssa-use, ssa-use
302 %4 = spv.IAdd %0, %1 : i32
303 %5 = spv.IAdd %2, %3 : vector<4xi32>
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Linalg/Utils/
H A DUtils.h454 IAdd, enumerator

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