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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcmov.ll241 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
254 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
276 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
291 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
297 ; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5
315 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
328 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
350 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
367 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
374 ; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dload-combine-like-or.ll11 ; CHECK-NEXT: [[I5:%.*]] = load i8, i8* [[PTR]], align 1
12 ; CHECK-NEXT: [[I6:%.*]] = zext i8 [[I5]] to i16
36 ; CHECK-NEXT: [[I6:%.*]] = zext i8 [[I5]] to i16
60 ; CHECK-NEXT: [[I6:%.*]] = zext i8 [[I5]] to i16
83 ; CHECK-NEXT: [[I5:%.*]] = add i16 [[I4]], 42
84 ; CHECK-NEXT: ret i16 [[I5]]
103 ; CHECK-NEXT: [[I5:%.*]] = add i16 [[I3]], 84
104 ; CHECK-NEXT: ret i16 [[I5]]
121 ; CHECK-NEXT: [[I5:%.*]] = add i16 [[I4]], 42
122 ; CHECK-NEXT: [[I6:%.*]] = add i16 [[I5]], [[I3]]
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dloop-range.mlir28 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
29 // CHECK: memref.store %[[I5]], %[[ARG0]]{{\[}}%[[I]]
61 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
62 // CHECK: memref.store %[[I5]], %[[ARG0]]{{\[}}%[[I]]
95 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
96 // CHECK: memref.store %[[I5]], %[[ARG0]]{{\[}}%[[I]]
127 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
128 // CHECK: memref.store %[[I5]], %[[ARG0]]{{\[}}%[[I3]]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dd83507-knowledge-retention-bug.ll12 ; CHECK-NEXT: [[I1:%.*]] = phi %0* [ %i0, [[BB:%.*]] ], [ [[I5:%.*]], [[BB3]] ]
15 ; CHECK-NEXT: [[I5]] = load %0*, %0** [[I4]], align 8
16 ; CHECK-NEXT: [[I2:%.*]] = icmp eq %0* [[I5]], null
/llvm-project-15.0.7/clang/test/Parser/
H A Dobjc-implementation-attrs.m33 @interface I5 @end interface
36 @implementation I5 { implementation
42 I5 *i5;
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/AArch64/
H A Dloops.ll15 ; CHECK-NEXT: [[I5:%.*]] = phi i32 [ [[TMP2:%.*]], [[BB15]] ], [ [[TMP0]], [[BB]] ]
23 ; CHECK-NEXT: [[I11:%.*]] = icmp eq i32 [[I5]], [[TMP1]]
24 ; CHECK-NEXT: [[I12:%.*]] = xor i32 [[I5]], 32
44 ; CHECK-NEXT: [[I27:%.*]] = phi i32 [ 0, [[BB]] ], [ [[I5]], [[BB21]] ], [ [[I5]], [[BB23]] ], […
120 ; CHECK-NEXT: [[I5:%.*]] = phi i32 [ [[I7:%.*]], [[BB4]] ], [ 0, [[BB:%.*]] ]
122 ; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
172 ; CHECK-NEXT: [[I5:%.*]] = phi i32 [ [[I7:%.*]], [[BB4]] ], [ 0, [[BB:%.*]] ]
174 ; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
225 ; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
276 ; CHECK-NEXT: [[I7]] = add i32 [[I5]], 1
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/infrastructure/
H A Dnolintnextline.cpp67 class I5 { I5(int x); }; class
/llvm-project-15.0.7/llvm/test/Transforms/StructurizeCFG/
H A Dinvert-condition.ll35 ; CHECK-NEXT: [[I5:%.*]] = icmp eq i32 [[ARG:%.*]], 0
36 ; CHECK-NEXT: [[I5_INV:%.*]] = xor i1 [[I5]], true
41 ; CHECK-NEXT: [[I7:%.*]] = phi i1 [ [[I5]], [[MAIN_BODY:%.*]] ], [ false, [[IF1]] ]
/llvm-project-15.0.7/clang/test/Index/
H A Doverrides.m87 @interface I5 : B5 interface
95 @implementation I5 implementation
118 // CHECK: overrides.m:95:17: ObjCImplementationDecl=I5:95:17 (Definition) Extent=[95:1 - 97:2]
H A Dindex-decls.m52 @class I5;
53 @interface I5 interface
86 // CHECK: [indexDeclaration]: kind: objc-property | name: c | USR: c:objc(cs)I5(cpy)c | lang: ObjC …
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dinterface-layout-64.m52 @interface I5 : I4 { interface
65 @interface I5 () interface in int
70 @implementation I5 implementation
/llvm-project-15.0.7/clang/test/SemaObjC/
H A Dproperty-12.m58 @interface I5 <P5> @end interface
59 @implementation I5 implementation
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dpr48641.ll10 ; CHECK-NEXT: [[I5:%.*]] = zext i8 [[I4]] to i32
11 ; CHECK-NEXT: [[I6:%.*]] = add nsw i32 [[I5]], [[ARG2:%.*]]
/llvm-project-15.0.7/llvm/test/Transforms/SROA/
H A Dstd-clamp.ll11 ; CHECK-NEXT: [[I5:%.*]] = fcmp fast olt float [[X:%.*]], [[LO:%.*]]
15 ; CHECK-NEXT: [[I9_SROA_SPECULATED:%.*]] = select i1 [[I5]], float [[LO]], float [[I9_SROA_SPECU…
/llvm-project-15.0.7/clang/test/Index/Core/
H A Dindex-source.m290 @interface I5 interface
294 @implementation I5 implementation
296 // CHECK: [[@LINE-1]]:13 | instance-property/ObjC | foo | c:objc(cs)I5(py)foo | <no-cgname> | Def,R…
297 // CHECK-NEXT: RelChild | I5 | c:objc(cs)I5
298 // CHECK-NEXT: RelAcc | _blahfoo | c:objc(cs)I5@_blahfoo
299 // CHECK: [[@LINE-4]]:13 | instance-method/acc-get/ObjC | foo | c:objc(cs)I5(im)foo | -[I5 foo] | D…
300 // CHECK-NEXT: RelChild | I5 | c:objc(cs)I5
301 // CHECK: [[@LINE-6]]:13 | instance-method/acc-set/ObjC | setFoo: | c:objc(cs)I5(im)setFoo: | -[I5 …
302 // CHECK-NEXT: RelChild | I5 | c:objc(cs)I5
303 // CHECK: [[@LINE-8]]:19 | field/ObjC | _blahfoo | c:objc(cs)I5@_blahfoo | <no-cgname> | Def,RelChi…
[all …]
/llvm-project-15.0.7/compiler-rt/lib/scudo/standalone/tests/
H A Dlist_test.cpp44 ListItem *I5 = nullptr, ListItem *I6 = nullptr) { in checkList() argument
61 if (I5) { in checkList()
62 EXPECT_EQ(L->front(), I5); in checkList()
/llvm-project-15.0.7/clang/test/CodeCompletion/
H A Dnamespace.cpp7 namespace I5 { } namespace
H A Dusing-namespace.cpp10 namespace I5 { } namespace
H A Dnamespace-alias.cpp10 namespace I5 { } namespace
H A Dusing.cpp10 namespace I5 { } namespace
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dpr22674.ll59 …%I5.096 = phi %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* [ …
60 …t %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* %I5.096 to i32*
73 …", %"class.llvm::Attribute.222.2021.3820.6133.6904.7675.8446.9474.9988.10245.18509"* %I5.096, i32 1
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dvec-move-24.ll21 %I5 = insertelement <16 x i8> %I4, i8 %Src, i32 5
22 %I6 = insertelement <16 x i8> %I5, i8 %Src, i32 6
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td108 // <opcode | I5 | rj | rd>
297 // < 0b0010101011 | I12 | rj | I5>
312 // < 0b00111000001011000 | rk | rj | I5>
356 // <0b0000011000 | I12 | rj | I5>
378 // <0b00000110010010011 | rk | rj | I5>
/llvm-project-15.0.7/clang/test/SemaObjCXX/
H A Dmessage.mm99 @interface I5 interface
104 void test_I5(I5 *i5, String s) {
/llvm-project-15.0.7/llvm/unittests/Transforms/Vectorize/
H A DVPlanTest.cpp81 VPInstruction *I5 = new VPInstruction(5, {}); in TEST() local
84 VPBB2.appendRecipe(I5); in TEST()
89 CHECK_ITERATOR(VPBB2, I4, I3, I5); in TEST()
108 VPInstruction *I5 = new VPInstruction(5, {}); in TEST() local
111 VPBB2.appendRecipe(I5); in TEST()
116 CHECK_ITERATOR(VPBB2, I3, I4, I5); in TEST()
124 CHECK_ITERATOR(VPBB2, I3, I5); in TEST()
681 VPInstruction *I5 = new VPInstruction(Instruction::Ret, {I4}); in TEST() local
684 VPBB2->appendRecipe(I5); in TEST()

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