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/llvm-project-15.0.7/mlir/test/Dialect/SCF/
H A Dloop-range.mlir27 // CHECK: %[[I4:.*]] = memref.load %[[ARG0]]{{\[}}%[[I]]
28 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
60 // CHECK: %[[I4:.*]] = memref.load %[[ARG0]]{{\[}}%[[I]]
61 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
94 // CHECK: %[[I4:.*]] = memref.load %[[ARG0]]{{\[}}%[[I]]
95 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
126 // CHECK: %[[I4:.*]] = memref.load %[[ARG0]]{{\[}}%[[I3]]
127 // CHECK: %[[I5:.*]] = arith.muli %[[I4]], %[[I4]] : i32
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dload-combine-like-or.ll10 ; CHECK-NEXT: [[I4:%.*]] = shl i16 [[I3]], 8
13 ; CHECK-NEXT: [[I7:%.*]] = or i16 [[I4]], [[I6]]
35 ; CHECK-NEXT: [[I5:%.*]] = load i8, i8* [[I4]], align 1
58 ; CHECK-NEXT: [[I4:%.*]] = shl i16 [[I3]], 9
61 ; CHECK-NEXT: [[I7:%.*]] = or i16 [[I4]], [[I6]]
82 ; CHECK-NEXT: [[I4:%.*]] = or i16 [[I3]], [[I2]]
83 ; CHECK-NEXT: [[I5:%.*]] = add i16 [[I4]], 42
120 ; CHECK-NEXT: [[I4:%.*]] = zext i8 [[LOWBITS:%.*]] to i16
121 ; CHECK-NEXT: [[I5:%.*]] = add i16 [[I4]], 42
138 ; CHECK-NEXT: [[I4:%.*]] = shl i16 42, 8
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dnoalias-ptr.ll54 ; CHECK-NEXT: [[I4:%.*]] = tail call noalias ptr @_Znam(i64 48) #[[ATTR2]]
58 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
85 ; CHECK-NEXT: [[I4:%.*]] = tail call noalias ptr @_Znam(i64 48) #[[ATTR2]]
89 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
120 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
151 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
186 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
221 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
256 ; CHECK-NEXT: call void @_ZdaPv(ptr [[I4]]) #[[ATTR3]]
284 ; CHECK-NEXT: [[I4:%.*]] = icmp eq ptr [[I1]], [[MSTACKDATA]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsink-not-into-another-hand-of-and.ll17 ; CHECK-NEXT: [[I4:%.*]] = select i1 [[TMP1]], i32 [[V3:%.*]], i32 [[V2:%.*]]
18 ; CHECK-NEXT: ret i32 [[I4]]
32 ; CHECK-NEXT: [[I4:%.*]] = select i1 [[TMP1]], i32 [[V5:%.*]], i32 [[V4:%.*]]
33 ; CHECK-NEXT: ret i32 [[I4]]
65 ; CHECK-NEXT: [[I4:%.*]] = select i1 [[I3]], i32 [[V2:%.*]], i32 [[V3:%.*]]
66 ; CHECK-NEXT: ret i32 [[I4]]
83 ; CHECK-NEXT: [[I4:%.*]] = and i1 [[I1]], [[I3]]
84 ; CHECK-NEXT: [[I5:%.*]] = select i1 [[I4]], i32 [[V4:%.*]], i32 [[V5:%.*]]
H A Dsink-not-into-another-hand-of-or.ll17 ; CHECK-NEXT: [[I4:%.*]] = select i1 [[TMP1]], i32 [[V3:%.*]], i32 [[V2:%.*]]
18 ; CHECK-NEXT: ret i32 [[I4]]
32 ; CHECK-NEXT: [[I4:%.*]] = select i1 [[TMP1]], i32 [[V5:%.*]], i32 [[V4:%.*]]
33 ; CHECK-NEXT: ret i32 [[I4]]
65 ; CHECK-NEXT: [[I4:%.*]] = select i1 [[I3]], i32 [[V2:%.*]], i32 [[V3:%.*]]
66 ; CHECK-NEXT: ret i32 [[I4]]
83 ; CHECK-NEXT: [[I4:%.*]] = or i1 [[I1]], [[I3]]
84 ; CHECK-NEXT: [[I5:%.*]] = select i1 [[I4]], i32 [[V4:%.*]], i32 [[V5:%.*]]
H A Dmerging-multiple-stores-into-successor.ll17 ; CHECK-NEXT: [[I4:%.*]] = load i16, i16* @var_0, align 2
25 ; CHECK-NEXT: [[I5:%.*]] = sext i16 [[I4]] to i64
32 ; CHECK-NEXT: store i16 [[I4]], i16* getelementptr inbounds ([0 x i16], [0 x i16]* @arr_4, i64 0…
33 ; CHECK-NEXT: [[I8:%.*]] = sext i16 [[I4]] to i32
36 ; CHECK-NEXT: store i16 [[I4]], i16* getelementptr inbounds ([0 x i16], [0 x i16]* @arr_4, i64 0…
H A Dctpop.ll391 ; CHECK-NEXT: [[I4:%.*]] = and i32 [[TMP2]], 1
392 ; CHECK-NEXT: ret i32 [[I4]]
405 ; CHECK-NEXT: [[I4:%.*]] = trunc i64 [[TMP2]] to i32
406 ; CHECK-NEXT: [[I5:%.*]] = and i32 [[I4]], 1
422 ; CHECK-NEXT: ret <2 x i32> [[I4]]
436 ; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], 3
437 ; CHECK-NEXT: ret i32 [[I4]]
452 ; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], 1
453 ; CHECK-NEXT: [[I5:%.*]] = xor i32 [[I4]], [[I2]]
471 ; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], 1
[all …]
/llvm-project-15.0.7/clang/test/Index/
H A Dindex-decls.m36 @interface I4 interface
42 @implementation I4 implementation
80 // CHECK: [indexDeclaration]: kind: objc-class | name: I4 | {{.*}} | loc: 36:12
81 …efinition) | loc: 43:13 | <parent>:: kind: objc-class | name: I4 | {{.*}} | container: [I4:42:17] …
H A Dcomplete-properties.m32 @interface I4 interface
36 @interface I4 () { interface in I4
37 I4 *Prop1; category
41 @implementation I4 { implementation
92 // CHECK-CC7: ObjCIvarDecl:{ResultType I4 *}{TypedText Prop1} (17)
/llvm-project-15.0.7/llvm/test/Transforms/SROA/
H A Dstd-clamp.ll9 ; CHECK-NEXT: [[I4:%.*]] = alloca float, align 4
10 ; CHECK-NEXT: store float [[HI:%.*]], ptr [[I4]], align 4
13 … [[I9_SROA_SPECULATE_LOAD_FALSE_SROA_SPECULATE_LOAD_TRUE:%.*]] = load float, ptr [[I4]], align 4
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcmov.ll399 ; 32-CMOV-DAG: addiu $[[I4:3]], $zero, 4
417 ; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4
422 ; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4
444 ; 32-CMOV-DAG: addiu $[[I4:3]], $zero, 4
462 ; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
465 ; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]]
468 ; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4
491 ; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4
496 ; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4
519 ; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4
[all …]
/llvm-project-15.0.7/clang-tools-extra/test/clang-tidy/infrastructure/
H A Dnolintnextline.cpp63 class I4 { I4(int x); }; class
/llvm-project-15.0.7/llvm/unittests/Transforms/Vectorize/
H A DVPlanTest.cpp83 VPBB2.appendRecipe(I4); in TEST()
86 I3->moveAfter(I4); in TEST()
89 CHECK_ITERATOR(VPBB2, I4, I3, I5); in TEST()
110 VPBB2.appendRecipe(I4); in TEST()
113 I3->moveBefore(VPBB2, I4->getIterator()); in TEST()
116 CHECK_ITERATOR(VPBB2, I3, I4, I5); in TEST()
121 I4->moveBefore(VPBB3, VPBB3.end()); in TEST()
125 CHECK_ITERATOR(VPBB3, I4); in TEST()
126 EXPECT_EQ(&VPBB3, I4->getParent()); in TEST()
683 VPBB2->appendRecipe(I4); in TEST()
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjC/
H A Dinterface-layout-64.m47 @interface I4 : I3 { interface
52 @interface I5 : I4 {
62 @implementation I4 implementation
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dd83507-knowledge-retention-bug.ll14 ; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds [[TMP0:%.*]], %0* [[I1]], i64 0, i32 0
15 ; CHECK-NEXT: [[I5]] = load %0*, %0** [[I4]], align 8
/llvm-project-15.0.7/clang/test/Index/Core/
H A Dindex-source.m266 @interface I4 interface
270 @implementation I4 { implementation
272 …// CHECK: [[@LINE-1]]:6 | field/ObjC | _blahfoo | c:objc(cs)I4@_blahfoo | <no-cgname> | Def,RelChi…
276 // CHECK-NEXT: RelChild | I4 | c:objc(cs)I4
277 // CHECK-NEXT: RelAcc | _blahfoo | c:objc(cs)I4@_blahfoo
278 // CHECK: [[@LINE-4]]:13 | instance-method/acc-get/ObjC | foo | c:objc(cs)I4(im)foo | -[I4 foo] | D…
279 // CHECK-NEXT: RelChild | I4 | c:objc(cs)I4
280 // CHECK: [[@LINE-6]]:13 | instance-method/acc-set/ObjC | setFoo: | c:objc(cs)I4(im)setFoo: | -[I4 …
281 // CHECK-NEXT: RelChild | I4 | c:objc(cs)I4
282 // CHECK: [[@LINE-8]]:19 | field/ObjC | _blahfoo | c:objc(cs)I4@_blahfoo | <no-cgname> | Ref | rel:…
[all …]
/llvm-project-15.0.7/clang/test/SemaObjC/
H A Dproperty-12.m53 @interface I4 <P4> @end interface
54 @implementation I4 implementation
/llvm-project-15.0.7/llvm/test/Transforms/SimplifyCFG/
H A Dpr48641.ll9 ; CHECK-NEXT: [[I4:%.*]] = load i8, i8* [[I3]], align 1
10 ; CHECK-NEXT: [[I5:%.*]] = zext i8 [[I4]] to i32
H A Dinvoke_unwind_lifetime.ll25 ; CHECK-NEXT: [[I4:%.*]] = alloca i32, align 4
26 ; CHECK-NEXT: [[I5:%.*]] = bitcast i32* [[I4]] to i8*
28 ; CHECK-NEXT: call void @escape(i32* [[I4]])
/llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/
H A Doffsetted-overlapping-stores.ll39 ; CHECK-NEXT: [[I4:%.*]] = bitcast float* [[I3]] to <2 x float>*
40 ; CHECK-NEXT: store <2 x float> zeroinitializer, <2 x float>* [[I4]], align 16
91 ; CHECK-NEXT: [[I4:%.*]] = bitcast float* [[I3]] to <2 x float>*
92 ; CHECK-NEXT: store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* [[I4]], a…
/llvm-project-15.0.7/clang/test/Parser/
H A Dobjc-implementation-attrs.m27 @interface I4 @end // expected-note {{annotate}} interface
28 @implementation I4 { implementation
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dnoclobber-barrier.ll31 ; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG]], i64 2
32 ; CHECK-NEXT: store i32 [[I3]], i32 addrspace(1)* [[I4]], align 4
73 ; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG]], i64 2
74 ; CHECK-NEXT: store i32 [[I3]], i32 addrspace(1)* [[I4]], align 4
120 ; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG]], i64 2
121 ; CHECK-NEXT: store i32 [[I3]], i32 addrspace(1)* [[I4]], align 4
168 ; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG]], i64 2
169 ; CHECK-NEXT: store i32 [[I3]], i32 addrspace(1)* [[I4]], align 4
209 ; CHECK-NEXT: store i32 [[I3]], i32 addrspace(1)* [[I4]], align 4
290 ; CHECK-NEXT: store i32 [[I3]], i32 addrspace(1)* [[I4]], align 4
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/X86/
H A Dpr35406.ll19 ; CHECK-NEXT: [[I4:%.*]] = load atomic i64, i64* [[P1:%.*]] unordered, align 8
20 ; CHECK-NEXT: [[I6:%.*]] = sub i64 [[I4]], -1
89 ; CHECK-NEXT: [[I4:%.*]] = load atomic i64, i64* [[P1:%.*]] unordered, align 8
90 ; CHECK-NEXT: [[I6:%.*]] = sub i64 [[I4]], [[INDVARS_IV_NEXT]]
/llvm-project-15.0.7/llvm/unittests/Transforms/Utils/
H A DSSAUpdaterBulkTest.cpp69 auto *I4 = cast<Instruction>(B.CreateSub(SubOp1, SubOp2)); in TEST() local
104 EXPECT_EQ(I4->getOperand(0), SubOp1); in TEST()
105 EXPECT_EQ(I4->getOperand(1), SubOp2); in TEST()
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/XCore/
H A Dno-vector-registers.ll17 ; CHECK-NEXT: [[I4:%.*]] = load double, double* [[ARRAYIDX4]], align 8
18 ; CHECK-NEXT: [[MUL5:%.*]] = fmul double [[I3]], [[I4]]

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