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/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DLowerSwitch.cpp55 int64_t Low, High; member
69 Ranges, R, [](IntRange A, IntRange B) { return A.High < B.High; }); in IsInRanges()
75 ConstantInt *High; member
167 if (Leaf.Low == Leaf.High) { in NewLeafBlock()
340 I->High = J->High; in Clusterify()
395 UpperBound = Cases.back().High; in ProcessSwitchInst()
419 APInt High = Cases.back().High->getValue(); in ProcessSwitchInst() local
440 int64_t High = I.High->getSExtValue(); in ProcessSwitchInst() local
449 LastRange.High = Low - 1; in ProcessSwitchInst()
457 int64_t N = High - Low + 1; in ProcessSwitchInst()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DSwitchLoweringUtils.cpp27 const APInt &HighCase = Clusters[Last].High->getValue(); in getJumpTableRange()
75 const APInt &Hi = Clusters[i].High->getValue(); in findJumpTables()
210 const APInt &High = Clusters[I].High->getValue(); in buildJumpTable() local
211 NumCmps += (Low == High) ? 1 : 2; in buildJumpTable()
382 APInt High = Clusters[Last].High->getValue(); in buildBitTests() local
383 assert(Low.slt(High)); in buildBitTests()
392 assert(TLI->rangeFitsInWord(Low, High, *DL) && in buildBitTests()
405 if (Low.isStrictlyPositive() && High.slt(BitWidth)) { in buildBitTests()
409 CmpRange = High; in buildBitTests()
413 CmpRange = High - Low; in buildBitTests()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DSwitchLoweringUtils.h44 const ConstantInt *Low, *High; member
52 static CaseCluster range(const ConstantInt *Low, const ConstantInt *High, in range()
57 C.High = High; in range()
63 static CaseCluster jumpTable(const ConstantInt *Low, const ConstantInt *High, in jumpTable()
68 C.High = High; in jumpTable()
74 static CaseCluster bitTests(const ConstantInt *Low, const ConstantInt *High, in bitTests()
79 C.High = High; in bitTests()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZMachineFunctionInfo.h53 void setSpillGPRRegs(Register Low, Register High, unsigned Offs) { in setSpillGPRRegs() argument
55 SpillGPRRegs.HighGPR = High; in setSpillGPRRegs()
63 void setRestoreGPRRegs(Register Low, Register High, unsigned Offs) { in setRestoreGPRRegs() argument
65 RestoreGPRRegs.HighGPR = High; in setRestoreGPRRegs()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DLangStandards.def213 HLSL, "High Level Shader Language",
217 HLSL, "High Level Shader Language 2015",
221 HLSL, "High Level Shader Language 2016",
225 HLSL, "High Level Shader Language 2017",
229 HLSL, "High Level Shader Language 2018",
233 HLSL, "High Level Shader Language 2021",
237 HLSL, "High Level Shader Language 202x",
/llvm-project-15.0.7/clang-tools-extra/clang-tidy/hicpp/
H A DLICENSE.TXT2 clang-tidy High-Integrity C++ Files
7 Any file referencing a High-Integrity C++ Coding guideline:
/llvm-project-15.0.7/llvm/test/tools/obj2yaml/Minidump/
H A Dbasic.yaml32 File Version High: 0x18191A1B
34 Product Version High: 0x20212223
41 File Date High: 0x3C3D3E3F
121 # CHECK-NEXT: File Version High: 0x18191A1B
123 # CHECK-NEXT: Product Version High: 0x20212223
130 # CHECK-NEXT: File Date High: 0x3C3D3E3F
/llvm-project-15.0.7/clang/test/Index/
H A Dcomplete-type-factors.m9 High
31 [a method:Red priority:High];
41 // CHECK-CC1: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (32)
54 // CHECK-CC2: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (65)
70 // CHECK-CC3: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (16)
86 // CHECK-CC4: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (65)
104 // CHECK-CC6: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (65)
120 // CHECK-CC7: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (65)
132 // CHECK-CC8: EnumConstantDecl:{ResultType enum Priority}{TypedText High} (16)
/llvm-project-15.0.7/llvm/test/Analysis/LoopAccessAnalysis/
H A Dmemcheck-off-by-one-error.ll15 ; (Low: %src High: (24 + %src))
22 ;CHECK: (Low: %op High: (32 + %op))
23 ;CHECK: (Low: %src High: (32 + %src))
H A Dnumber-of-memchecks.ll98 ; CHECK-NEXT: (Low: %c High: (80 + %c))
102 ; CHECK-NEXT: (Low: %a High: (42 + %a))
106 ; CHECK-NEXT: (Low: %b High: (40 + %b))
170 ; CHECK-NEXT: (Low: %c High: (80 + %c))
174 ; CHECK-NEXT: (Low: %a High: (42 + %a))
178 ; CHECK-NEXT: (Low: %b High: (40 + %b))
249 ; CHECK-NEXT: (Low: ((2 * %offset) + %a) High: (10000 + (2 * %offset) + %a))
252 ; CHECK-NEXT: (Low: %a High: (10000 + %a))
255 ; CHECK-NEXT: (Low: (20000 + %a) High: (30000 + %a))
H A Dforked-pointers.ll25 ; CHECK-NEXT: (Low: %Dest High: (400 + %Dest))
29 ; CHECK-NEXT: (Low: %Base1 High: (400 + %Base1))
32 ; CHECK-NEXT: (Low: %Base2 High: (400 + %Base2))
84 ; CHECK-NEXT: (Low: %Dest High: (400 + %Dest))
87 ; CHECK-NEXT: (Low: %Preds High: (400 + %Preds))
90 ; CHECK-NEXT: (Low: %Base2 High: (400 + %Base2))
93 ; CHECK-NEXT: (Low: %Base1 High: (400 + %Base1))
171 ; CHECK-NEXT: (Low: %Dest High: (800 + %Dest))
232 ; CHECK-NEXT: (Low: %Dest High: (399 + %Dest))
293 ; CHECK-NEXT: (Low: %Dest High: (100 + %Dest))
[all …]
H A Dmemcheck-store-vs-alloc-size.ll9 ;CHECK: (Low: %op High: (27 + %op))
10 ;CHECK: (Low: %src High: (27 + %src))
/llvm-project-15.0.7/lld/test/ELF/
H A Dgdb-index-ranges.s8 # CHECK-NEXT: Low/High address = [0x201120, 0x201121) (Size: 0x1), CU id = 0
9 # CHECK-NEXT: Low/High address = [0x201121, 0x201123) (Size: 0x2), CU id = 0
H A Dgdb-index-base-addr.s8 # CHECK-NEXT: Low/High address = [0x201120, 0x201121) (Size: 0x1), CU id = 0
9 # CHECK-NEXT: Low/High address = [0x201123, 0x201126) (Size: 0x3), CU id = 0
H A Dgdb-index-icf.s11 # CHECK-NEXT: Low/High address = [0x1001, 0x1002) (Size: 0x1), CU id = 0
12 # CHECK-NEXT: Low/High address = [0x1001, 0x1002) (Size: 0x1), CU id = 1
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.h141 MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false);
146 bool High = false);
/llvm-project-15.0.7/bolt/test/X86/
H A Dgdbindex.test27 ; CHECK-NEXT: Low/High address = [0x20117c, 0x201187) (Size: 0xb), CU id = 0
28 ; CHECK-NEXT: Low/High address = [0x201188, 0x201193) (Size: 0xb), CU id = 1
/llvm-project-15.0.7/llvm/test/DebugInfo/
H A Ddwarfdump-dump-gdbindex.test23 ; CHECK-NEXT: Low/High address = [0x4000e8, 0x4000f3) (Size: 0xb), CU id = 0
24 ; CHECK-NEXT: Low/High address = [0x4000f3, 0x4000fe) (Size: 0xb), CU id = 1
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUOperandSyntax.rst348 High and low 32 bits of *trap base address* may be accessed as separate registers:
377 High and low 32 bits of *trap memory address* may be accessed as separate registers:
406 High and low 32 bits of *flat scratch* address may be accessed as separate registers:
412 flat_scratch_hi High 32 bits of *flat scratch* address register.
442 High and low 32 bits of *xnack mask* may be accessed as separate registers:
448 xnack_mask_hi High 32 bits of *xnack mask* register.
450 [xnack_mask_hi] High 32 bits of *xnack mask* register (an SP3 syntax).
482 vcc_hi High 32 bits of *vector condition code* register.
521 High and low 32 bits of *execute mask* may be accessed as separate registers:
527 exec_hi High 32 bits of *execute mask* register.
[all …]
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVVMIntrRange.cpp61 static bool addRangeMetadata(uint64_t Low, uint64_t High, CallInst *C) { in addRangeMetadata() argument
70 ConstantAsMetadata::get(ConstantInt::get(Int32Ty, High))}; in addRangeMetadata()
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DInlineAsm.h373 unsigned High = Flag >> 16; in hasRegClassConstraint() local
376 if (!High) in hasRegClassConstraint()
378 RC = High - 1; in hasRegClassConstraint()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp465 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction() local
468 TmpInst.addOperand(MCOperand::createReg(High)); in HexagonProcessInstruction()
542 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction() local
544 MO.setReg(High); in HexagonProcessInstruction()
554 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction() local
556 MO.setReg(High); in HexagonProcessInstruction()
568 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction() local
570 MO.setReg(High); in HexagonProcessInstruction()
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dload-slice.ll14 ; Low High
17 ; High slice starts at 4 (base + 4-bytes) and is 4-bytes aligned.
85 ; Low High
88 ; High slice starts at 6 (base + 6-bytes) and is 2-bytes aligned.
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dinlineasm-constraint-m-2.ll41 ; "M": High-order word of a double word.
62 ; High-order part.
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/hicpp/
H A Dno-assembler.rst8 Inline assembler is forbidden by the `High Integrity C++ Coding Standard

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