Searched refs:HiSrc (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 2538 static int isElementRotate(int &LoSrc, int &HiSrc, ArrayRef<int> Mask) { in isElementRotate() argument
2550 HiSrc = -1; in isElementRotate()
2579 int &TargetSrc = StartIdx < 0 ? HiSrc : LoSrc; in isElementRotate()
2593 assert((LoSrc >= 0 || HiSrc >= 0) && in isElementRotate()
2693 int LoSrc, HiSrc; in lowerVECTOR_SHUFFLE() local
2694 int Rotation = isElementRotate(LoSrc, HiSrc, Mask); in lowerVECTOR_SHUFFLE()
2701 if (HiSrc >= 0) { in lowerVECTOR_SHUFFLE()
2702 HiV = HiSrc == 0 ? V1 : V2; in lowerVECTOR_SHUFFLE()
2948 int LoSrc, HiSrc; in isShuffleMaskLegal() local
2949 return (isElementRotate(LoSrc, HiSrc, M) > 0) || in isShuffleMaskLegal()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 10848 SDValue HiSrc = extract128BitVector(SrcVec, 16, DAG, DL); in createVariablePermute() local
10853 DAG.getNode(X86ISD::VPPERM, DL, MVT::v16i8, LoSrc, HiSrc, LoIdx), in createVariablePermute()
10854 DAG.getNode(X86ISD::VPPERM, DL, MVT::v16i8, LoSrc, HiSrc, HiIdx)); in createVariablePermute()
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