Searched refs:HiOpc (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsSEInstrInfo.h | 101 unsigned LoOpc, unsigned HiOpc,
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| H A D | MipsSEInstrInfo.cpp | 730 unsigned HiOpc, in expandPseudoMTLoHi() argument
741 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); in expandPseudoMTLoHi()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 184 unsigned HiOpc = HighRegInst.getOpcode(); in areCombinableOperations() local
197 verifyOpc(HiOpc); in areCombinableOperations()
200 if (HiOpc == Hexagon::V6_vassign || LoOpc == Hexagon::V6_vassign) in areCombinableOperations()
201 return HiOpc == LoOpc; in areCombinableOperations()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4025 unsigned HiOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32; in EmitInstrWithCustomInserter() local
4027 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1); in EmitInstrWithCustomInserter()
4097 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in EmitInstrWithCustomInserter() local
4099 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()
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| H A D | SIInstrInfo.cpp | 6809 unsigned HiOpc = IsAdd ? AMDGPU::V_ADDC_U32_e64 : AMDGPU::V_SUBB_U32_e64; in splitScalar64BitAddSub() local
6811 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub()
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