Searched refs:HiHalf (Results 1 – 5 of 5) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAGHVX.cpp | 629 return OpRef(R.OpN & (Undef | Index | HiHalf)); in hi()
646 HiHalf = 0x40000000, enumerator
647 Whole = LoHalf | HiHalf,
722 assert((OpN & Whole) == LoHalf || (OpN & Whole) == HiHalf); in print()
1074 assert(Part == OpRef::LoHalf || Part == OpRef::HiHalf); in materialize()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1859 MachineInstr *HiHalf = in computeBase() local
1866 (void)HiHalf; in computeBase()
1867 LLVM_DEBUG(dbgs() << " "; HiHalf->dump();); in computeBase()
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| H A D | SIInstrInfo.cpp | 6739 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp() local
6754 Worklist.insert(&HiHalf); in splitScalar64BitUnaryOp()
6810 MachineInstr *HiHalf = in splitScalar64BitAddSub() local
6829 legalizeOperands(*HiHalf, MDT); in splitScalar64BitAddSub()
6879 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp() local
6893 Worklist.insert(&HiHalf); in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 4098 MachineInstr *HiHalf = in EmitInstrWithCustomInserter() local
4112 TII->legalizeOperands(*HiHalf); in EmitInstrWithCustomInserter()
5690 SDValue HiHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BCVec, in lowerINSERT_VECTOR_ELT() local
5694 SDValue HiVec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i16, HiHalf); in lowerINSERT_VECTOR_ELT()
5706 DAG.getBuildVector(MVT::v2i32, SL, { InsHalf, HiHalf }) : in lowerINSERT_VECTOR_ELT()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 4858 Register HiHalf = MRI.createVirtualRegister(&Mips::GPR32RegClass); in emitLDR_D() local
4875 .addDef(HiHalf) in emitLDR_D()
4883 .addUse(HiHalf); in emitLDR_D()
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