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/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drv32zhinxmin-invalid.s5 …: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Ha…
15 …n # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer)
H A Drv64zhinx-invalid.s4 …: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Ha…
H A Drv64zhinxmin-invalid.s4 …: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Ha…
H A Drv32zfhmin-invalid.s25 … # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-…
H A Drv32zhinx-invalid.s5 fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-…
/llvm-project-15.0.7/clang/include/clang/AST/
H A DPrettyPrinter.h71 PolishForDeclaration(false), Half(LO.Half), in PrintingPolicy()
230 unsigned Half : 1; member
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCV.td66 "'Zfhmin' (Half-Precision Floating-Point Minimal)",
70 "'Zfhmin' (Half-Precision Floating-Point Minimal)">;
74 "'Zfh' (Half-Precision Floating-Point)",
78 "'Zfh' (Half-Precision Floating-Point)">;
83 "'Zfh' (Half-Precision Floating-Point) or "
103 "'Zhinxmin' (Half Float in Integer Minimal)",
107 "'Zhinxmin' (Half Float in Integer Minimal)">;
111 "'Zhinx' (Half Float in Integer)",
115 "'Zhinx' (Half Float in Integer)">;
120 "'Zhinx' (Half Float in Integer) or "
[all …]
/llvm-project-15.0.7/clang/lib/Sema/
H A DOpenCLBuiltins.td485 Float, Double, Half] in {
494 foreach Type = [Float, Double, Half] in {
742 def : Builtin<name, [GenTypeHalfVecNoScalar, GenTypeHalfVecNoScalar, Half, Half], Attr.Const>;
754 def : Builtin<name, [GenTypeHalfVecNoScalar, Half, Half, GenTypeHalfVecNoScalar], Attr.Const>;
785 …def : Builtin<name, [VectorType<Half, VSize>, VectorType<Half, VSize>, VectorType<Half, VSize>], A…
821 def : Builtin<name, [Int, Half, Half], Attr.Const>;
861 … def : Builtin<name, [VectorType<Half, VSize>, Size, PointerType<ConstType<Half>, AS>], Attr.Pure>;
875 def : Builtin<name, [Void, VectorType<Half, VSize>, Size, PointerType<Half, AS>]>;
1180 [Half, PointerType<VolatileType<AtomicHalf>, addrspace>, Half], extension_fp16>;
1188 [Half, PointerType<VolatileType<AtomicHalf>, addrspace>, Half], extension_fp16>;
[all …]
/llvm-project-15.0.7/compiler-rt/lib/hwasan/
H A Dhwasan_globals.cpp28 ElfW(Half) phnum) { in CheckCodeModel()
52 ElfW(Half) phnum) { in HwasanGlobalsFor()
H A Dhwasan_interface_internal.h31 ElfW(Half) phnum);
35 ElfW(Half) phnum);
H A Dhwasan_globals.h45 ElfW(Half) phnum);
/llvm-project-15.0.7/mlir/tools/mlir-vulkan-runner/
H A Dvulkan-runtime-wrappers.cpp147 DECLARE_BIND_MEMREF(1, int16_t, Half)
148 DECLARE_BIND_MEMREF(2, int16_t, Half)
149 DECLARE_BIND_MEMREF(3, int16_t, Half)
/llvm-project-15.0.7/clang/lib/Lex/
H A DPreprocessingRecord.cpp217 size_t Half; in findBeginLocalPreprocessedEntity() local
227 Half = Count/2; in findBeginLocalPreprocessedEntity()
229 std::advance(I, Half); in findBeginLocalPreprocessedEntity()
234 Count = Count - Half - 1; in findBeginLocalPreprocessedEntity()
236 Count = Half; in findBeginLocalPreprocessedEntity()
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_solaris.h45 ElfW(Half) dlpi_phnum;
/llvm-project-15.0.7/llvm/tools/llvm-reduce/deltas/
H A DDelta.cpp129 int Half = (C.Begin + C.End) / 2; in increaseGranularity() local
130 NewChunks.push_back({C.Begin, Half}); in increaseGranularity()
131 NewChunks.push_back({Half + 1, C.End}); in increaseGranularity()
/llvm-project-15.0.7/llvm/test/CodeGen/XCore/
H A Dunaligned_store.ll12 ; Half word aligned store.
H A Dunaligned_load.ll12 ; Half word aligned load.
/llvm-project-15.0.7/llvm/lib/DebugInfo/PDB/Native/
H A DSymbolCache.cpp406 size_t Half; in findPublicSymbolBySectOffset() local
409 Half = Count / 2; in findPublicSymbolBySectOffset()
410 It += Half; in findPublicSymbolBySectOffset()
421 Count -= Half + 1; in findPublicSymbolBySectOffset()
423 Count = Half; in findPublicSymbolBySectOffset()
/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/
H A DRegisterValueTest.cpp22 TEST(RegisterValueTest, Half) { in TEST() argument
/llvm-project-15.0.7/llvm/unittests/DebugInfo/DWARF/
H A DDWARFDebugLineTest.cpp447 {{LineTable::Half, LineTable::Long}, {Version, LineTable::Half}});
474 {5, LineTable::Half}, // version
788 {{0x1234, LineTable::Half}, {0x56, LineTable::Byte}});
1343 LT.setCustomPrologue({{2, LineTable::Long}, {0, LineTable::Half}});
1345 LT2.setCustomPrologue({{2, LineTable::Long}, {1, LineTable::Half}});
1412 LT.setCustomPrologue({{2, LineTable::Long}, {0, LineTable::Half}});
1414 LT2.setCustomPrologue({{2, LineTable::Long}, {1, LineTable::Half}});
1486 LT.addStandardOpcode(DW_LNS_fixed_advance_pc, {{55, LineTable::Half}});
1919 ValueAndLengths{{0x500, LineTable::Half}},
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86Schedule.td453 defm WriteCvtPH2PS : X86SchedWritePair<ReadAfterVecXLd>; // Half -> Float size conversion.
454 defm WriteCvtPH2PSY : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (YMM).
455 defm WriteCvtPH2PSZ : X86SchedWritePair<ReadAfterVecYLd>; // Half -> Float size conversion (ZMM).
457 def WriteCvtPS2PH : SchedWrite; // // Float -> Half size conversion.
458 def WriteCvtPS2PHY : SchedWrite; // // Float -> Half size conversion (YMM).
459 def WriteCvtPS2PHZ : SchedWrite; // // Float -> Half size conversion (ZMM).
460 def WriteCvtPS2PHSt : SchedWrite; // // Float -> Half + store size conversion.
461 def WriteCvtPS2PHYSt : SchedWrite; // // Float -> Half + store size conversion (YMM).
462 def WriteCvtPS2PHZSt : SchedWrite; // // Float -> Half + store size conversion (ZMM).
/llvm-project-15.0.7/libclc/
H A DREADME.TXT17 * 9.6: Half Precision Floating-Point
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Disel-shuff-single.ll3 ; Perfect shuffle with single input vector. Half of it first needs to be
/llvm-project-15.0.7/llvm/test/Transforms/SimpleLoopUnswitch/
H A Dexponential-nontrivial-unswitch-nested.ll56 ; Half unswitched loop nests, with unscaled4 and div1 it gets less depth1 loops unswitched
63 ; Half unswitched loop nests, with unscaled4 and div2 it gets more depth1 loops unswitched
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsics.h122 Half, enumerator

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