Searched refs:HWS (Results 1 – 3 of 3) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/MCA/Stages/ |
| H A D | ExecuteStage.cpp | 44 if (Scheduler::Status S = HWS.isAvailable(IR)) { in isAvailable()
58 HWS.issueInstruction(IR, Used, Pending, Ready); in issueInstruction()
81 InstRef IR = HWS.select(); in issueReadyInstructions()
87 IR = HWS.select(); in issueReadyInstructions()
99 HWS.cycleEvent(Freed, Executed, Pending, Ready); in cycleStart()
132 uint64_t Mask = HWS.analyzeResourcePressure(Insts); in cycleEnd()
143 HWS.analyzeDataDependencies(RegDeps, MemDeps); in cycleEnd()
191 HWS.instructionCheck(IR); in execute()
201 bool IsReadyInstruction = HWS.dispatch(IR); in execute()
220 if (!HWS.mustIssueImmediately(IR)) in execute()
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| /llvm-project-15.0.7/llvm/lib/MCA/ |
| H A D | Context.cpp | 44 auto HWS = std::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline() local
51 std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis); in createDefaultPipeline()
58 addHardwareUnit(std::move(HWS)); in createDefaultPipeline()
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| /llvm-project-15.0.7/llvm/include/llvm/MCA/Stages/ |
| H A D | ExecuteStage.h | 29 Scheduler &HWS; variable
52 : HWS(S), NumDispatchedOpcodes(0), NumIssuedOpcodes(0), in ExecuteStage()
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