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/llvm-project-15.0.7/llvm/tools/llvm-xray/
H A Dxray-color-helper.cpp152 static double interpolateHue(double H0, double H1, double T) { in interpolateHue() argument
153 double D = H1 - H0; in interpolateHue()
154 if (H0 > H1) { in interpolateHue()
155 std::swap(H0, H1); in interpolateHue()
162 return H0 + T * (H1 - H0); in interpolateHue()
164 H0 = H0 + 360; in interpolateHue()
165 return std::fmod(H0 + T * (H1 - H0) + 720, 360); in interpolateHue()
/llvm-project-15.0.7/lldb/test/API/functionalities/postmortem/FreeBSDKernel/
H A Dvmcore-arm64-minidump.bz21minidump FreeBSD/arm64�������� ����j������������
/llvm-project-15.0.7/llvm/test/Transforms/FixIrreducible/
H A Dnested.ll251 ; CHECK-NEXT: br label [[H0:%.*]]
252 ; CHECK: H0:
273 ; CHECK-NEXT: br i1 [[PRED7:%.*]], label [[EXIT:%.*]], label [[H0]]
284 br label %H0
286 H0:
317 br i1 %Pred7, label %exit, label %H0
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/autohvx/
H A Darith.ll226 ; CHECK: v[[H0:[0-9]+]]:[[L0:[0-9]+]].h = vmpy(v0.b,v1.b)
227 ; CHECK: vshuffe(v[[H0]].b,v[[L0]].b)
234 ; CHECK: v[[H0:[0-9]+]]:[[L0:[0-9]+]].h = vmpy(v0.b,v1.b)
235 ; CHECK: vshuffe(v[[H0]].b,v[[L0]].b)
/llvm-project-15.0.7/clang/lib/Headers/
H A Dhexagon_types.h670 short H0(void) { in H0() function
761 HEXAGON_Vect64C H0(short h) { in H0() function
1106 short H0(void) { in H0() function
1153 HEXAGON_Vect32C H0(short h) { in H0() function
1897 short H0(void) { in H0() function
1988 Q6Vect64C H0(short h) { in H0() function
2333 short H0(void) { in H0() function
2380 Q6Vect32C H0(short h) { in H0() function
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64CallingConvention.td102 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
103 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
139 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
140 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
213 CCIfType<[f16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
214 CCIfType<[bf16], CCAssignToReg<[H0, H1, H2, H3, H4, H5, H6, H7]>>,
H A DAArch64CallingConvention.cpp26 static const MCPhysReg HRegList[] = {AArch64::H0, AArch64::H1, AArch64::H2,
H A DAArch64AsmPrinter.cpp1135 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31) in emitFMov0()
1136 DestReg = AArch64::D0 + (DestReg - AArch64::H0); in emitFMov0()
H A DAArch64RegisterInfo.td294 def H0 : AArch64Reg<0, "h0", [B0]>, DwarfRegAlias<B0>;
329 def S0 : AArch64Reg<0, "s0", [H0]>, DwarfRegAlias<B0>;
H A DAArch64FastISel.cpp2940 { AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, in fastLowerArguments()
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dforeach-multiclass.td138 defm H0 : H<g>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp266 {codeview::RegisterId::ARM64_H0, AArch64::H0}, in initLLVMToCVRegMapping()
H A DAArch64InstPrinter.cpp1747 case 16: Base = AArch64::H0; break; in printZPRasFPR()
/llvm-project-15.0.7/polly/lib/External/isl/imath/tests/
H A Dqtodec.tc22 qtodec:4/5861792533,21,10,0:0.00000014H0
/llvm-project-15.0.7/llvm/test/Transforms/VectorCombine/AArch64/
H A Dselect-shuffle.ll411 ; CHECK-NEXT: [[H0:%.*]] = getelementptr <4 x i32>, ptr [[DST:%.*]], i32 0
412 ; CHECK-NEXT: store <4 x i32> [[T0]], ptr [[H0]], align 16
472 ; CHECK-NEXT: [[H0:%.*]] = getelementptr <4 x i32>, ptr [[DST:%.*]], i32 0
473 ; CHECK-NEXT: store <4 x i32> [[T0]], ptr [[H0]], align 16
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2991 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0, Chain); in getVectorCmp() local
2997 SDValue HRes = DAG.getNode(Opcode, DL, VTs, Chain, H0, H1); in getVectorCmp()
3000 SDValue Chains[6] = { H0.getValue(1), L0.getValue(1), in getVectorCmp()
3007 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1); in getVectorCmp()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1603 case 16: Base = AArch64::H0; break; in addFPRasZPRRegOperands()
4650 (ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) || in isMatchingOrAlias()