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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A DtargetLoweringGeneric.ll3 ; Gather non-machine specific tests for the transformations in
H A Davx512-gather-scatter-intrin-deprecated.ll78 ;; Integer Gather/Scatter
H A Davx512-gather-scatter-intrin.ll72 ;; Integer Gather/Scatter
/llvm-project-15.0.7/llvm/test/DebugInfo/
H A Ddwarfdump-accel.test4 Gather some DIE indexes to verify the accelerator table contents.
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/X86/
H A Dx86-pr39099.ll10 ; (For SKX, Gather is not supported by the compiler for chars, therefore
/llvm-project-15.0.7/mlir/test/Integration/Dialect/Vector/CPU/
H A Dtest-gather.mlir56 // Gather tests.
/llvm-project-15.0.7/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp3498 return LoadsState::Gather; in canVectorizeLoads()
3508 return LoadsState::Gather; in canVectorizeLoads()
3569 return LoadsState::Gather; in canVectorizeLoads()
3949 TreeEntry *Gather = nullptr; in canReorderOperands() local
3960 Gather = TE; in canReorderOperands()
3967 if (Gather) in canReorderOperands()
3968 GatherOps.push_back(Gather); in canReorderOperands()
4184 for (TreeEntry *Gather : GatherOps) { in reorderBottomToTop()
4193 OrderedEntries.remove(Gather); in reorderBottomToTop()
5031 case LoadsState::Gather: in buildTree_rec()
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/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVScheduleV.td257 // 16.4. Vector Register Gather Instructions
476 // 16.4. Vector Register Gather Instructions
H A DRISCVISelLowering.cpp2062 return Gather; in matchSplatAsGather()
2064 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in matchSplatAsGather()
2190 return Gather; in lowerBUILD_VECTOR()
2685 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
2881 SDValue Gather; in lowerVECTOR_SHUFFLE() local
2894 Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V1, in lowerVECTOR_SHUFFLE()
2921 Gather = DAG.getNode(GatherVXOpc, DL, ContainerVT, V2, in lowerVECTOR_SHUFFLE()
2923 Gather, VL); in lowerVECTOR_SHUFFLE()
2929 SelectMask, Gather, VL); in lowerVECTOR_SHUFFLE()
2933 return convertFromScalableVector(VT, Gather, DAG, Subtarget); in lowerVECTOR_SHUFFLE()
[all …]
/llvm-project-15.0.7/clang/docs/
H A DRefactoringEngine.rst189 - Gather the set of options and define a command-line / visual interface
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td2128 // Gather load, vector + imm, 32-bit element size
2132 // Gather load, vector + imm, 64-bit element size
2136 // Gather load, 64-bit element size
2143 // Gather load, 32-bit scaled offset
2148 // Gather load, 32-bit unpacked unscaled offset
H A DAArch64SVEInstrInfo.td57 // Gather loads - node definitions
1448 // Gather prefetch using scaled 32-bit offsets, e.g.
1455 // Gather prefetch using unpacked, scaled 32-bit offsets, e.g.
1462 // Gather prefetch using scaled 64-bit offsets, e.g.
1469 // Gather prefetch using 32/64-bit pointers with offset, e.g.
/llvm-project-15.0.7/lldb/docs/
H A Dlldb-platform-packets.txt157 // Gather information about a process running on the target
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td97 // Vector Gather and scatter
H A DVEInstrVec.td284 // Section 8.9.13 - VGT (Vector Gather)
287 // Section 8.9.14 - VGTU (Vector Gather Upper)
290 // Section 8.9.15 - VGTL (Vector Gather Lower)
/llvm-project-15.0.7/llvm/docs/
H A DVectorizers.rst262 Scatter / Gather
/llvm-project-15.0.7/mlir/include/mlir/Dialect/LLVMIR/
H A DLLVMIntrinsicOps.td382 /// Create a call to Masked Gather intrinsic.
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DVariableNames.rst303 #. Gather feedback and refine the process as appropriate.
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsPPC.def545 // P10 Vector Gather Every N-th Bit built-in.
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2091 // Gather loads: scalar base + vector offsets
2109 // Gather loads: vector base + scalar offset
H A DIntrinsicsPowerPC.td657 // P10 Vector Gather Every Nth Bit Builtin.
/llvm-project-15.0.7/openmp/runtime/src/
H A Dkmp_itt.inl393 1. Gather -- primary thread waits for all worker threads to arrive; each
/llvm-project-15.0.7/mlir/include/mlir/Dialect/Tosa/IR/
H A DTosaOps.td1566 let summary = "Gather operation,";
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86.td581 // Gather is available since Haswell (AVX2 set). So technically, we can
H A DX86InstrInfo.td366 // Gather mem operands
400 // Gather mem operands
433 // Gather mem operands

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