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/llvm-project-15.0.7/lldb/test/API/functionalities/scripted_process/
H A DTestScriptedProcess.py130 GPRs = None
134 GPRs = regs
137 self.assertTrue(GPRs, "Invalid General Purpose Registers Set")
138 self.assertGreater(GPRs.GetNumChildren(), 0)
139 for idx, reg in enumerate(GPRs, start=1):
H A Dstack_core_scripted_process.py164 GPRs = None
168 GPRs = regs
171 if not GPRs:
174 for reg in GPRs:
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dasm-17.ll6 ; Test i32 GPRs.
17 ; Test i64 GPRs.
63 ; Test clobbers of GPRs and CC.
H A Dfp-move-13.ll21 ; Test 128-bit moves from GPRs to VRs. i128 isn't a legitimate type,
34 ; Test 128-bit moves from VRs to GPRs, with the same restriction as f2.
H A Dargs-08.ll5 ; Up to four integer return values fit into GPRs.
32 ; Up to four floating-point return values fit into GPRs.
H A Dfp-move-02.ll1 ; Test moves between FPRs and GPRs. The 32-bit cases test the z10
11 ; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
57 ; Test 64-bit moves from GPRs to FPRs.
65 ; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type,
80 ; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
90 ; Test 64-bit moves from FPRs to GPRs.
98 ; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
H A Dframe-05.ll1 ; Test saving and restoring of call-saved GPRs.
5 ; This function should require all GPRs, but no other spill slots. The caller
81 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
188 ; This function should use all call-clobbered GPRs but no call-saved ones.
H A Dframe-25.ll4 ; where no GPRs are saved / restored.
H A Dint-move-01.ll1 ; Test moves between GPRs.
H A Dframe-06.ll7 ; This function should require all GPRs, but no other spill slots. The caller
78 ; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs
185 ; This function should use all call-clobbered GPRs but no call-saved ones.
H A Dfp-move-10.ll1 ; Test moves between FPRs and GPRs for z13 and above.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dinlineasm-operand-implicit-cast.ll86 ; Check support for returning several floats in GPRs with matching float inputs
99 ; Check support for returning several double in GPRs with matching double input
112 ; Check support for returning several float in specific GPRs with matching
125 ; Check support for returning several double in specific GPRs with matching
236 ; Check support for returning several floats in GPRs with matching float inputs
254 ; Check support for returning several double in GPRs with matching double input
272 ; Check support for returning several float in specific GPRs with matching
290 ; Check support for returning several double in specific GPRs with matching
H A D2013-04-16-AAPCS-C5-vs-VFP.ll4 ; Our purpose: make NSAA != SP, and only after start to use GPRs, then pass
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dwrong-stack-slot-rv64.mir5 # This test checks that we are assigning the right stack slot to GPRs and to
7 # between slots for GPRs and VRs.
H A Dwrong-stack-slot-rv32.mir5 # These tests check that we are assigning the right stack slot to GPRs and to
7 # between slots for GPRs and VRs.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A DFrames-stack-floor.ll28 ; 288 bytes = 18*8 (FPRs) + 18*8 (GPRs, GPR13 reserved);
31 ; 220 bytes = 18*8 (FPRs) + 19*4 (GPRs);
H A Dprolog_vec_spills.mir17 # Use mtvsrdd to save two GPRs in a single instruction
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmmx-copy-gprs.ll6 ; This test should use GPRs to copy the mmx value, not MMX regs. Using mmx regs,
H A Dmmx-arg-passing-x86-64.ll5 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
H A Dmmx-arg-passing.ll9 ; On Darwin x86-64, v1i64 values are passed in 64-bit GPRs.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td259 // GPRs without the PC. Some ARM instructions do not allow the PC in
271 // GPRs without the PC but with APSR. Some instructions allow accessing the
282 // GPRs without the SP register. Used for BXAUT and AUTG
292 // GPRs without the PC and SP registers but with APSR. Used by CLRM instruction.
339 // GPRs without the PC and SP but with APSR_NZCV.Some instructions allow
529 // Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
530 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
538 // Register class representing a pair of even-odd GPRs.
543 // Register class representing a pair of even-odd GPRs, except (R12, SP).
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb/
H A D2011-06-16-NoGPRs.ll5 ; register, but we cannot have live GPRs in thumb mode because we don't know how
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Davoid-predspill.ll3 ; This checks that predicate registers are moved to GPRs instead of spilling
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dframelayout-unaligned-fp.ll4 ; of callee-saved GPRs as well as an odd number of callee-saved FPRs are
/llvm-project-15.0.7/llvm/test/DebugInfo/PowerPC/
H A Dlive-debug-vars-subreg-offset.ll17 ; // Clobber all GPRs.

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