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Searched refs:GPR_32 (Results 1 – 5 of 5) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86GenRegisterBankInfo.def57 INSTR_3OP(BREAKDOWN(PMI_GPR32, 1)) // 6: GPR_32
H A DX86CallingConv.td37 list<Register> GPR_32 = [];
50 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];
77 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];
95 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
174 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td266 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
2678 GPR_32, ISA_MIPS1;
2681 GPR_32, ISA_MIPS1;
2710 "sge\t$rd, $rs, $imm">, GPR_32;
2714 GPR_32;
2728 GPR_32;
2739 "sgt\t$rd, $rs, $imm">, GPR_32;
2743 GPR_32;
2757 GPR_32;
2771 GPR_32;
[all …]
H A DMips32r6InstrInfo.td957 def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
958 def SELNEZ : R6MMR6Rel, SELNEZ_ENC, SELNEZ_DESC, ISA_MIPS32R6, GPR_32;
1001 ISA_MIPS32R6, GPR_32;
1004 def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
1008 ISA_MIPS32R6, GPR_32;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6598 static const MCPhysReg GPR_32[] = {// 32-bit registers. in CC_AIX() local
6630 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6657 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) in CC_AIX()
6678 if (unsigned Reg = State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32)) { in CC_AIX()
6731 ArrayRef<MCPhysReg> GPRs = IsPPC64 ? GPR_64 : GPR_32; in CC_AIX()
7181 static const MCPhysReg GPR_32[] = {PPC::R3, PPC::R4, PPC::R5, PPC::R6, in LowerFormalArguments_AIX() local
7186 const unsigned NumGPArgRegs = array_lengthof(IsPPC64 ? GPR_64 : GPR_32); in LowerFormalArguments_AIX()
7197 : MF.addLiveIn(GPR_32[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_AIX()