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/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Ddivrem.ll24 ; GPR64-TRAP - Same as TRAP and GPR64 combined
43 ; GPR64: div $2, $4, $5
44 ; GPR64-TRAP: teq $5, $zero, 7
70 ; GPR64: mod $2, $4, $5
71 ; GPR64-TRAP: teq $5, $zero, 7
97 ; GPR64: divu $2, $4, $5
98 ; GPR64-TRAP: teq $5, $zero, 7
123 ; GPR64: modu $2, $4, $5
166 ; GPR64-DAG: div $2, $4, $5
208 ; GPR64-DAG: divu $2, $4, $5
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td235 (STLRX GPR64:$val, GPR64sp:$ptr)>;
243 (STRXroX GPR64:$val, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend)>;
400 def : Pat<(stxr_1 GPR64:$val, GPR64sp:$addr),
402 def : Pat<(stxr_2 GPR64:$val, GPR64sp:$addr),
404 def : Pat<(stxr_4 GPR64:$val, GPR64sp:$addr),
406 def : Pat<(stxr_8 GPR64:$val, GPR64sp:$addr),
407 (STXRX GPR64:$val, GPR64sp:$addr)>;
454 def : Pat<(stlxr_1 GPR64:$val, GPR64sp:$addr),
511 (ins GPR64:$addr, GPR64:$desired, GPR64:$new), []>,
519 (ins GPR64:$addr, GPR64:$desiredLo, GPR64:$desiredHi,
[all …]
H A DAArch64InstrGISel.td271 def : Pat<(atomic_cmp_swap_8 GPR64:$addr, GPR32:$desired, GPR32:$new),
272 (CMP_SWAP_8 GPR64:$addr, GPR32:$desired, GPR32:$new)>;
274 def : Pat<(atomic_cmp_swap_16 GPR64:$addr, GPR32:$desired, GPR32:$new),
275 (CMP_SWAP_16 GPR64:$addr, GPR32:$desired, GPR32:$new)>;
278 (CMP_SWAP_32 GPR64:$addr, GPR32:$desired, GPR32:$new)>;
280 def : Pat<(atomic_cmp_swap_64 GPR64:$addr, GPR64:$desired, GPR64:$new),
281 (CMP_SWAP_64 GPR64:$addr, GPR64:$desired, GPR64:$new)>;
284 def : Pat<(int_aarch64_stlxp GPR64:$lo, GPR64:$hi, GPR64:$addr),
285 (STLXPX GPR64:$lo, GPR64:$hi, GPR64:$addr)>;
286 def : Pat<(int_aarch64_stxp GPR64:$lo, GPR64:$hi, GPR64:$addr),
[all …]
H A DAArch64InstrInfo.td1706 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
1707 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
1769 def : Pat<(int_aarch64_udiv GPR64:$Rn, GPR64:$Rm), (UDIVXr GPR64:$Rn, GPR64:$Rm)>;
1771 def : Pat<(int_aarch64_sdiv GPR64:$Rn, GPR64:$Rm), (SDIVXr GPR64:$Rn, GPR64:$Rm)>;
2186 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
2371 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
2376 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
2381 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
8307 def : Pat<(i64x8 (LS64_BUILD GPR64:$x0, GPR64:$x1, GPR64:$x2, GPR64:$x3,
8308 GPR64:$x4, GPR64:$x5, GPR64:$x6, GPR64:$x7)),
[all …]
H A DAArch64SVEInstrInfo.td1433 (RegRegInst sve_prfop:$prfop, PPR_3b:$gp, GPR64:$base, GPR64:$index)>;
2458 …def _reg_reg_z : Pat<(Ty (Load (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp), (SVEDup0Unde…
2459 (RegRegInst PPR:$gp, GPR64:$base, GPR64:$offset)>;
2505 … def _reg_reg : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp)),
2506 (RegRegInst ZPR:$vec, PPR:$gp, GPR64:$base, GPR64:$offset)>;
2601 def : Pat<(Ty (Load GPR64:$base)),
2680 def : Pat<(Ty (Load (PredTy PPR:$gp), (AddrCP GPR64:$base, GPR64:$offset), MemVT)),
2768 def : Pat<(Ty (Load (PredTy PPR:$gp), (AddrCP GPR64:$base, GPR64:$offset), MemVT)),
2812 def : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp), MemVT),
2904 def : Pat<(nxv2i64 (vector_insert (nxv2i64 ZPR:$vec), GPR64:$src, GPR64:$index)),
[all …]
H A DAArch64InstrFormats.td2065 [(set GPR64:$dst, (op GPR64:$Rd, opcode, (i64 0)))]>,
2077 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
2079 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
2294 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
2301 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
2303 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
2325 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
2632 GPR64, GPR64, GPR64, 0>;
2729 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
2739 GPR64, GPR64, GPR64, 0>;
[all …]
H A DAArch64RegisterInfo.td148 // GPR64/GPR64sp for use by the coalescer.
164 let AltOrders = [(rotl GPR64, 8)];
192 // GPR32/GPR64 but with zero-register substitution enabled.
193 // TODO: Roll this out to GPR32/GPR64/GPR32all/GPR64all.
197 def GPR64z : RegisterOperand<GPR64> {
235 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
236 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
237 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
238 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
239 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
[all …]
H A DSVEInstrFormats.td797 def : Pat<(i64 (op GPR64:$Rn, (nxv16i1 PPRAny:$Pg))),
799 def : Pat<(i64 (op GPR64:$Rn, (nxv8i1 PPRAny:$Pg))),
801 def : Pat<(i64 (op GPR64:$Rn, (nxv4i1 PPRAny:$Pg))),
803 def : Pat<(i64 (op GPR64:$Rn, (nxv2i1 PPRAny:$Pg))),
869 : I<(outs GPR64:$Rd), (ins PPRAny:$Pg, pprty:$Pn),
980 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
1491 def _D : sve_int_perm_insrs<0b11, asm, ZPR64, GPR64>;
2558 : I<(outs GPR64:$Rd), (ins simm6_32b:$imm6),
5006 : I<(outs pprty:$Pd), (ins GPR64:$Rn, GPR64:$Rm),
5398 def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
[all …]
H A DAArch64SMEInstrInfo.td143 (MSR 0xde85, GPR64:$val)>;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td420 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
821 def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))),
822 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
824 def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))),
825 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
827 def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))),
828 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>,
830 def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))),
860 def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
861 (DSUBu GPR64:$lhs, GPR64:$rhs)>, ISA_MIPS3, GPR_64;
[all …]
H A DMipsCondMov.td208 defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
214 defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>,
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
220 defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>,
229 defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>,
239 defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>,
257 defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>,
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll15 …rch=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
16 …rch=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
17 …rch=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR64,DMTC1,NOT-R6
116 ; GPR64-DAG: ori $2, $[[T0]], 1
131 ; GPR64-DAG: daddiu $[[T1:[0-9]+]], $[[T0]], 1
132 ; GPR64-DAG: dsll $2, $[[T1]], 32
147 ; GPR64-DAG: ori $[[T0:[0-9]+]], $zero, 32769
148 ; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 16
149 ; GPR64-DAG: daddiu $[[T0:[0-9]+]], $[[T0]], -32767
150 ; GPR64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 17
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/ABI/X86/
H A DABIX86.cpp154 #define GPR64(n) \ macro
185 GPR64(8), GPR64(9), GPR64(10), GPR64(11), in makeBaseRegMap()
186 GPR64(12), GPR64(13), GPR64(14), GPR64(15), in makeBaseRegMap()
/llvm-project-15.0.7/llvm/test/TableGen/
H A Drc-weight-override.td10 def GPR_64_W0 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
15 def GPR_64_W1 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
20 def GPR_64_W8 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
H A Ddag-isel-complexpattern.td14 def GPR64 : RegisterClass<"TestTarget", [i64], 64, (add REG64)>;
28 let InOperandList = (ins GPR64:$addr);
H A Dambiguous-composition.td78 class GPR64<string n, GPR32 low> : TestReg<n, [low]> {
82 class GPR128<string n, GPR64 low> : TestReg<n, [low]> {
87 def G0D : GPR64<"g0d", G0S>;
H A DRegisterInfoEmitter-regcost-tuple.td45 def GPR64 : RegisterTuples<[sub0, sub1],
59 def GPR_64 : MyClass<64, [v2i32], (add GPR64)>;
H A DAllowDuplicateRegisterNames.td40 def GPR64 : RegisterClass<"Arch", [i64], 64, (add
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td67 class GPR64<bits<16> num, string n, GPR32 low, GPR32 high>
75 class GPR128<bits<16> num, string n, GPR64 low, GPR64 high>
86 def R#I#D : GPR64<I, "r"#I, !cast<GPR32>("R"#I#"L"), !cast<GPR32>("R"#I#"H")>,
91 def R#I#Q : GPR128<I, "r"#I, !cast<GPR64>("R"#!add(I, 1)#"D"),
92 !cast<GPR64>("R"#I#"D")>;
H A DSystemZFrameLowering.cpp313 unsigned GPR64, bool IsImplicit) { in addSavedGPR() argument
316 Register GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32); in addSavedGPR()
317 bool IsLive = MBB.isLiveIn(GPR64) || MBB.isLiveIn(GPR32); in addSavedGPR()
319 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive)); in addSavedGPR()
321 MBB.addLiveIn(GPR64); in addSavedGPR()
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterContextFreeBSD_powerpc.cpp55 } GPR64; typedef
223 return sizeof(GPR64); in GetGPRSize()
H A DRegisterInfos_powerpc.h185 #define GPR GPR64
197 #define GPR GPR64
/llvm-project-15.0.7/llvm/test/TableGen/Common/
H A Dreg-with-subregs-common.td48 def GPR64 : RegisterTuples<[sub0, sub1],
136 def GPR_64 : RegisterClass<"", [v2i32], 64, (add GPR64)>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-dead-register-def-bug.ll6 ; E.g. dead %x1 = MOVi64imm 2, implicit-def %w1; %x1:GPR64, %w1:GPR32
H A Daarch64-vector-pcs.mir6 # Padding of GPR64-registers is needed to ensure 16 byte alignment of
7 # the stack pointer after the GPR64/FPR64 block (which is also needed

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