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/llvm-project-15.0.7/llvm/test/TableGen/Common/
H A Dreg-with-subregs-common.td45 def GPR32 : RegisterClass<"TestTarget", [i32], 32,
49 [(decimate (shl GPR32, 0), 1),
50 (decimate (shl GPR32, 1), 1)
55 (decimate (shl GPR32, 0), 1),
56 (decimate (shl GPR32, 1), 1),
57 (decimate (shl GPR32, 2), 1),
58 (decimate (shl GPR32, 3), 1)
63 (decimate (shl GPR32, 0), 1),
64 (decimate (shl GPR32, 1), 1),
65 (decimate (shl GPR32, 2), 1),
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DGlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td6 def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
7 def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
34 …GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$…
62 …GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$…
81 …GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (InstThreeOperands…
91 def : Pat<(i32 (select GPR32:$cond, GPR32:$src1, GPR32:$src2)),
92 (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>;
95 (i32 (sub GPR32:$src1, GPR32:$src2)),
97 (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>;
100 (i32 (sub GPR32:$src1, GPR32:$src2)),
[all …]
H A DGlobalISelEmitterMatchTableOptimizerSameOperand.td6 def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
7 def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>;
20 def : Pat<(i32 (select GPR32:$cond, GPR32:$src1, GPR32:$src2)),
21 (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>;
23 def : Pat<(i32 (select (i32 (setcc GPR32:$cond, (i32 0), (OtherVT SETEQ))),
24 (i32 (add GPR32:$src1, GPR32:$const)),
25 GPR32:$src1)),
26 (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$const)>;
H A Daddress-space-patfrags.td41 let InOperandList = (ins GPR32:$src0, GPR32:$src1);
46 let InOperandList = (ins GPR32:$src0, GPR32:$src1);
67 (pat_frag_b GPR32:$src),
68 (inst_b GPR32:$src)
88 (inst_a GPR32:$src)
107 (truncstore GPR32:$src0, GPR32:$src1),
108 (inst_c GPR32:$src0, GPR32:$src1)
117 (store GPR32:$src0, GPR32:$src1),
118 (inst_d GPR32:$src0, GPR32:$src1)
129 (truncstorei16_addrspace GPR32:$src0, GPR32:$src1),
[all …]
H A DGlobalISelEmitterVariadic.td8 def ONE : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
9 def TWO : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
17 def : Pat<(build_vector GPR32:$src1),
18 (ONE GPR32:$src1)> {
22 def : Pat<(build_vector GPR32:$src1, GPR32:$src2),
23 (TWO GPR32:$src1, GPR32:$src2)>;
33 // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1) => (ONE:{ *:[i32] } GPR…
47 …build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (TWO:{ *:[i32] } G…
H A Dgisel-physreg-input.td13 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
39 // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *…
48 def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
49 [(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> {
67 // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:…
76 def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL),
77 [(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> {
82 // def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0),
83 // [(set GPR32:$dst, (add GPR32:$src0, SPECIAL:$special))]> {
H A DGlobalISelEmitter.td41 let MIOperandInfo = (ops GPR32, GPR32);
322 (INSN3 GPR32:$src1, GPR32:$src2b, GPR32:$src2a,
526 def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4),
528 (sub (sub GPR32:$src1, GPR32:$src2), (sub GPR32:$src3, GPR32:$src4)))]>,
744 def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
823 def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3),
1031 def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
1032 [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
1057 def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32:$src, GPR32:$src))…
1107 def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1),
[all …]
H A DGlobalISelEmitterSkippedPatterns.td15 let MIOperandInfo = (ops GPR32, GPR32);
22 def INSN : I<(outs GPR32:$dst), (ins GPR32:$src1, complex:$src2), []>;
27 def : Pat<(add (complex_rr GPR32:$x, GPR32:$y),
28 (complex_rr GPR32:$x, GPR32:$z)),
29 (INSN GPR32:$z, complex:$y)>;
H A DGlobalISelEmitter-PR39045.td23 let OutOperandList = (outs GPR32:$dst);
24 let InOperandList = (ins GPR32:$src);
27 let OutOperandList = (outs GPR32:$dst);
28 let InOperandList = (ins GPR32:$src);
32 (pat_frag_a GPR32:$src),
33 (inst_a GPR32:$src)
37 (pat_frag_b GPR32:$src),
38 (inst_b GPR32:$src)
H A DGlobalISelEmitterOverloadedPtr.td21 …*:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<<P:Predicate_frag_anyptr>> => (ANYLOA…
24 def ANYLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
25 [(set GPR32:$dst, (load GPR32:$src1))]>;
34 def : Pat<(frag_anyptr GPR32:$src),
35 (p0 (ANYLOAD GPR32:$src))>;
H A DContextlessPredicates.td18 def INSN : I<(outs GPR32:$dst), (ins GPR32Op:$src1, GPR32Op:$src2), []>;
20 def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
21 (INSN GPR32:$ptr, GPR32:$val)>;
39 …:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (…
65 …:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>> => (…
H A DGlobalISelEmitter-setcc.td11 def FCMPOEQ : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1),
12 [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, SETOEQ)))]>;
18 def ICMPEQ : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32:$src1),
19 [(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>;
23 def FCMP_NOTCC : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1),
24 [(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, i32)))]>;
H A DRegisterInfoEmitter-regcost-tuple.td43 def GPR32 : MyClass<32, [i32], (sequence "S%u", 0, 15)>;
46 [(decimate (shl GPR32, 0), 1),
47 (decimate (shl GPR32, 1), 1)
52 (decimate (shl GPR32, 0), 1),
53 (decimate (shl GPR32, 1), 1),
54 (decimate (shl GPR32, 2), 1),
55 (decimate (shl GPR32, 3), 1)
H A DGlobalISelEmitter-zero-reg.td21 def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>;
33 …-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>>…
41 def : Pat<(i32 (load GPR32:$src)),
42 (INST GPR32:$src)>;
H A DGlobalISelEmitter-immarg-literal-pattern.td19 def CAT0 : I<(outs GPR32:$dst), (ins GPR32:$src0), []>;
20 def CAT1 : I<(outs GPR32:$dst), (ins GPR32:$src0), []>;
51 (CAT0 GPR32:$src0)
60 (CAT1 GPR32:$src0)
H A DGlobalISelEmitter-output-discard.td7 def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag),
15 …, i32:{ *:[i32] }:$src1) => (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i…
26 (ADD_CO GPR32:$src0, GPR32:$src1)
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrAtomics.td184 GPR32:$val),
185 (STRBBroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend)>;
188 GPR32:$val),
203 (STRHHroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend)>;
221 (STRWroW GPR32:$val, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend)>;
498 def CMP_SWAP_8 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
499 (ins GPR64:$addr, GPR32:$desired, GPR32:$new), []>,
502 def CMP_SWAP_16 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
503 (ins GPR64:$addr, GPR32:$desired, GPR32:$new), []>,
506 def CMP_SWAP_32 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCInstrInfo.td160 (ins GPR32:$B, GPR32:$C),
165 (ins GPR32:$B, GPR32:$C),
375 (outs GPR32:$B), (ins GPR32:$C),
398 (outs GPR32:$B), (ins GPR32:$C, GPR32:$B2, cmovpred:$cc),
558 F16_COMPACT<0b0, (outs GPR32:$g), (ins GPR32:$h),
577 F16_COMPACT<0b1, (outs GPR32:$r), (ins GPR32:$h, immU<5>:$u5),
731 F16_OP_HREG<0b000, (outs GPR32:$b_s3), (ins GPR32:$h),
747 F16_OP_HREG<0b111,(outs GPR32:$b_s3), (ins GPR32:$h),
763 F16_OP_HREG<0b100, (outs GPR32:$b_s3), (ins GPR32:$h),
919 (outs GPR32:$A, GPR32:$addrout),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Ddivrem.ll23 ; GPR32-TRAP - Same as TRAP and GPR32 combined
40 ; GPR32: div $2, $4, $5
41 ; GPR32-TRAP: teq $5, $zero, 7
67 ; GPR32: mod $2, $4, $5
68 ; GPR32-TRAP: teq $5, $zero, 7
94 ; GPR32: divu $2, $4, $5
95 ; GPR32-TRAP: teq $5, $zero, 7
120 ; GPR32: modu $2, $4, $5
121 ; GPR32-TRAP: teq $5, $zero, 7
159 ; GPR32-DAG: div $2, $4, $5
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/GICombinerEmitter/
H A Dmatch-tree.td14 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
22 def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
23 def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
24 def SUB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
25 def MUL : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>;
26 def TRUNC : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
27 def SEXT : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
28 def ZEXT : I<(outs GPR32:$dst), (ins GPR32:$src1), []>;
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCondMov.td199 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
202 defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>, INSN_MIPS4_32_NOT_32R6_64R6;
204 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
212 defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>,
216 defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>,
218 defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>,
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
232 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
[all …]
H A DMicroMipsInstrInfo.td1223 def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
1224 (SLLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1230 def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
1231 (SRLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1235 def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1236 (SRAV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1247 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1293 defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
1295 defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
1304 defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td192 (ins GPR32:$dst, GPR32:$src, brtarget:$BrDst),
278 (ins GPR32:$src2, GPR32:$src),
285 [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>;
317 def NEG_32: NEG_RR<BPF_ALU, BPF_NEG, (outs GPR32:$dst), (ins GPR32:$src),
571 (ins GPR:$lhs, GPR:$rhs, i64imm:$imm, GPR32:$src, GPR32:$src2),
581 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2),
586 (ins GPR32:$lhs, i32imm:$rhs, i32imm:$imm, GPR32:$src, GPR32:$src2),
591 (ins GPR32:$lhs, GPR32:$rhs, i32imm:$imm, GPR:$src, GPR:$src2),
717 [(set GPR32:$dst, (OpNode ADDRri:$addr, GPR32:$val))]> {
773 [(set GPR32:$dst, (OpNode ADDRri:$addr,GPR32:$val))]> {
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/FixedLenDecoderEmitter/
H A Dconflict.td10 def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
22 def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
26 def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/llvm-ir/
H A Dret.ll11 …rch=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
12 …rch=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,NOT-R6
14 …-march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,GPR32,MTHC1,R6C
113 ; GPR32-DAG: ori $3, $[[T0]], 1
114 ; GPR32-DAG: addiu $2, $zero, 0
128 ; GPR32-DAG: ori $2, $[[T0]], 1
129 ; GPR32-DAG: addiu $3, $zero, 0
142 ; GPR32-DAG: lui $[[T0:[0-9]+]], 1
143 ; GPR32-DAG: lui $[[T1:[0-9]+]], 2
144 ; GPR32-DAG: ori $2, $[[T0]], 1
[all …]

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