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Searched refs:GP (Results 1 – 25 of 57) sorted by relevance

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/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dextender.s14 memb(GP + #56) = r0
29 memh(GP + #56) = r0
44 memw(GP + #56) = r0
62 memb(GP + #56) = r0.new
81 memh(GP + #56) = r0.new
116 memd(GP + #56) = r1:0
131 r0 = memb(GP + #56)
146 r0 = memub(GP + #56)
161 r0 = memh(GP + #56)
176 r0 = memuh(GP + #56)
[all …]
H A Dtwo-extenders.s28 # -------------------------- Use GP and non GP notation
76 # -------------------------- Use GP and non GP notation
H A Dload-GPRel.s3 # Check encoding bits for GP-relative loads.
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dtls-static.ll42 ; STATICGP32: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
43 ; STATICGP32: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
47 ; STATICGP64: daddiu $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
48 ; STATICGP64: ld $1, %gottprel(t2)($[[GP]])
52 ; STATIC32: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
53 ; STATIC32: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
60 ; STATIC64: daddiu $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
61 ; STATIC64: ld $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
H A Dglobal-pointer-reg.ll15 ; CHECK: addu $[[GP:[0-9]+]], $[[R1]], $25
16 ; CHECK: lw ${{[0-9]+}}, %call16(foo2)($[[GP]])
/llvm-project-15.0.7/lld/test/ELF/
H A Dmips-reginfo.s16 # CHECK-NEXT: Value: 0x[[GP:[0-9A-F]+]]
19 # CHECK-NEXT: GP: 0x[[GP]]
H A Dmips-gp-ext.s42 # G - (GP - .got)
47 # foo - GP
63 # G - (GP - .got)
68 # foo - GP
H A Dmips-options.s32 # CHECK-NEXT: Value: 0x[[GP:[0-9A-F]+]]
36 # CHECK-NEXT: GP: 0x[[GP]]
H A Dmips-64-gprel-so.s2 # Check setup of GP relative offsets in a function's prologue.
H A Dmips-64-got.s26 # GOT: {{.*}}: [[GP:[0-9a-f]+]] {{.*}} _gp
30 # GOT-NEXT: Canonical gp value: [[GP]]
H A Dmips-gprel32-relocs-gp0.s15 # REL: GP: 0x0
H A Dmips-gp-lowest.s3 # to the GP-relative section with the lowest address.
H A Dmips-non-zero-gp0.s45 # GPVAL: GP: 0x0
/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Datomic-ops-libcall.cl31 // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(1)* {{%[0-9]+}} to i8 addrspace(4)*
32 …// SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]…
36 // SPIR: %[[GP:[0-9]+]] = addrspacecast i8 addrspace(3)* {{%[0-9]+}} to i8 addrspace(4)*
37 …// SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]…
41 // SPIR: %[[GP:[0-9]+]] = addrspacecast i8* {{%[0-9]+}} to i8 addrspace(4)*
42 …// SPIR: call void @__opencl_atomic_store_4(i8 addrspace(4)* noundef %[[GP]], i32 noundef {{%[0-9]…
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCRegisterInfo.td46 def GP : Core<26, "%gp",["%r26"]>, DwarfRegNum<[26]>;
64 (add (sequence "R%u", 0, 25), GP, FP, SP, ILINK, R30, BLINK, (sequence "R%u", 32, 63))> {
65 let AltOrders=[(add (sequence "R%u", 0, 25), GP, FP, SP, ILINK, R30, BLINK)];
H A DARCCallingConv.td40 def CSR_ARC : CalleeSavedRegs<(add (sequence "R%u", 13, 25), GP, FP)>;
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dxcore-stringtype.c65 int* GP; variable
67 return I? EP : GP; in pointerType()
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/ELF/
H A Dmips-options-sec.test10 # CHECK-NEXT: GP: 0x807060504030201
18 # CHECK-NEXT: GP: 0x0
38 # NAME-ERR-FOUND-NEXT: GP: 0x807060504030201
46 # NAME-ERR-FOUND-NEXT: GP: 0x0
131 # KIND-NEXT: GP: 0x0
H A Dmips-reginfo.test8 # OPTIONS-NEXT: GP: 0x807060504030201
31 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8 ] ## GP register value.
/llvm-project-15.0.7/llvm/lib/Transforms/IPO/
H A DInternalize.cpp69 ExternalNames, [&](GlobPattern &GP) { return GP.match(GV.getName()); }); in operator ()() argument
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp177 Reserved.set(Mips::GP); in getReservedRegs()
235 Reserved.set(Mips::GP); in getReservedRegs()
H A DMipsRegisterInfo.td115 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
149 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
294 K0, K1, GP, SP, FP, RA)>;
314 K0, K1, GP, SP, FP, RA)>;
492 def GP32 : RegisterClass<"Mips", [i32], 32, (add GP)>, Unallocatable;
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dnon-integral-pointers.ll56 ; CHECK-NEXT: [[DOTPRE:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[GP:%.*]], align 8
80 ; CHECK-NEXT: [[DOTPRE:%.*]] = load i8*, i8* addrspace(4)* [[GP:%.*]], align 8
/llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIInfo.cpp88 return ArePtrs64bit() ? Mips::GP_64 : Mips::GP; in GetGlobalPtr()
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Delf-bigendian.ll30 ; See that at least first 3 instructions are correct: GP prologue

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