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Searched refs:GDS (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/libclc/amdgcn/lib/mem_fence/
H A Dfence.cl7 // [12:8] LGKM -- LDS, GDS, Konstant (SMRD), Messages
9 // [6:4] -- exports, GDS, and mem write
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A Dgfx8_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx1030_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx7_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx10_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx940_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx9_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx90a_vaddr_f20ee4.rst13 An offset from the start of GDS/LDS memory.
H A Dgfx1030_waitcnt.rst22 \- 13:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63
H A Dgfx7_waitcnt.rst22 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
H A Dgfx8_waitcnt.rst22 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
H A Dgfx9_waitcnt.rst22 \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
H A Dgfx10_waitcnt.rst22 \- 13:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..63
H A Dgfx940_waitcnt.rst22 \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
H A Dgfx90a_waitcnt.rst22 \- 11:8 LGKM_CNT: LDS, GDS, Constant and Message count. 0..15
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp73 GDS = 1u << 3, enumerator
80 ATOMIC = GLOBAL | LDS | SCRATCH | GDS,
83 ALL = GLOBAL | LDS | SCRATCH | GDS | OTHER,
150 SIAtomicAddrSpace::GDS)) == SIAtomicAddrSpace::NONE) { in SIMemOpInfo()
680 return SIAtomicAddrSpace::GDS; in toSIAtomicAddrSpace()
1022 if ((AddrSpace & SIAtomicAddrSpace::GDS) != SIAtomicAddrSpace::NONE) { in insertWait()
1331 SIAtomicAddrSpace::GDS)) != SIAtomicAddrSpace::NONE) && in insertWait()
1930 if ((AddrSpace & SIAtomicAddrSpace::GDS) != SIAtomicAddrSpace::NONE) { in insertWait()
H A DGCNHazardRecognizer.cpp154 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS() local
156 if (MI.getOperand(GDS).getImm()) in isSendMsgTraceDataOrGDS()
H A DSIInstrInfo.td1225 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dgds-allocation.ll31 ; The LDS alignment shouldn't change offset of GDS.
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUModifierSyntax.rst180 Specifies whether to use GDS or LDS memory (LDS is the default).
185 gds Use GDS memory.
H A DAMDGPUUsage.rst671 …Region 2 N/A GDS 32 *not implem…
726 The region address space uses the hardware Global Data Store (GDS). All
1924 ``DW_ADDR_AMDGPU_region`` 0x8000 Region (GDS)
1931 available for use for the AMD extension for access to the hardware GDS memory
1968 ``DW_ASPACE_AMDGPU_region`` 0x02 32 32 Region (GDS)
3763 Region N/A GDS 32 *not implemented
14012 memory or GDS.
14367 For full list of supported instructions, refer to "LDS/GDS instructions" in ISA
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td473 [llvm_anyptr_ty, // LDS or GDS ptr