Searched refs:Fma3 (Results 1 – 2 of 2) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 3945 auto Fma3 = B.buildFMA(S32, Fma2, Fma1, Mul, Flags); in legalizeFDIV32() local
3946 auto Fma4 = B.buildFMA(S32, NegDivScale0, Fma3, NumeratorScaled, Flags); in legalizeFDIV32()
3954 .addUse(Fma3.getReg(0)) in legalizeFDIV32()
4007 auto Fma3 = B.buildFMA(S64, Fma1, Fma2, Fma1, Flags); in legalizeFDIV64() local
4008 auto Mul = B.buildFMul(S64, DivScale1.getReg(0), Fma3, Flags); in legalizeFDIV64()
4034 .addUse(Fma3.getReg(0)) in legalizeFDIV64()
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| H A D | SIISelLowering.cpp | 9066 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, in LowerFDIV32() local
9069 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, in LowerFDIV32()
9070 NumeratorScaled, Fma3, Flags); in LowerFDIV32()
9097 {Fma4, Fma1, Fma3, Scale}, Flags); in LowerFDIV32()
9128 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1); in LowerFDIV64() local
9129 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3); in LowerFDIV64()
9164 Fma4, Fma3, Mul, Scale); in LowerFDIV64()
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