| /llvm-project-15.0.7/clang/test/Driver/ |
| H A D | cl-denorms-are-zero.cl | 5 // Fast FMAF, but slow f32 denormals
9 // Fast F32 denormals, but slow FMAF
13 // Fast F32 denormals and fast FMAF
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| /llvm-project-15.0.7/llvm/lib/Transforms/Utils/ |
| H A D | BypassSlowDivision.cpp | 425 QuotRemWithBB Fast = createFastBB(SuccessorBB); in insertFastDivAndRem() local
426 QuotRemPair Result = createDivRemPhiNodes(Fast, Long, SuccessorBB); in insertFastDivAndRem()
428 Builder.CreateCondBr(CmpV, Fast.BB, SuccessorBB); in insertFastDivAndRem()
438 QuotRemWithBB Fast = createFastBB(SuccessorBB); in insertFastDivAndRem() local
440 QuotRemPair Result = createDivRemPhiNodes(Fast, Slow, SuccessorBB); in insertFastDivAndRem()
443 Builder.CreateCondBr(CmpV, Fast.BB, Slow.BB); in insertFastDivAndRem()
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| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | fast-isel-cmp-branch.ll | 4 ; Fast-isel mustn't add a block to the MBB successor/predecessor list twice.
18 ; Fast-isel shouldn't try to look through the compare because it's in a
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| H A D | O0-pipeline.ll | 44 ; CHECK-NEXT: Fast Tile Register Preconfigure
47 ; CHECK-NEXT: Fast Register Allocator
48 ; CHECK-NEXT: Fast Tile Register Configure
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| H A D | virtreg-physreg-def-regallocfast.mir | 2 # Fast regalloc used to not collect physical register definitions
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | GCNNSAReassign.cpp | 83 NSA_Status CheckNSA(const MachineInstr &MI, bool Fast = false) const;
162 GCNNSAReassign::CheckNSA(const MachineInstr &MI, bool Fast) const { in CheckNSA()
188 if (!Fast) { in CheckNSA()
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| /llvm-project-15.0.7/llvm/include/llvm/IR/ |
| H A D | CallingConv.h | 42 Fast = 8, enumerator
|
| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | CGPassBuilderOption.h | 24 enum class RegAllocType { Default, Basic, Fast, Greedy, PBQP }; enumerator
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| H A D | TargetOptions.h | 37 Fast, // Enable fusion of FP ops wherever it's profitable. enumerator
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kCallingConv.td | 53 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_M68k_Fast>>,
105 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_M68k_Fast>>,
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| /llvm-project-15.0.7/llvm/lib/Transforms/Coroutines/ |
| H A D | CoroEarly.cpp | 50 CB.setCallingConv(CallingConv::Fast); in lowerResumeOrDestroy()
120 NoopFn->setCallingConv(CallingConv::Fast); in lowerCoroNoop()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.cpp | 55 cl::values(clEnumValN(RegBankSelect::Mode::Fast, "regbankselect-fast",
87 if (OptMode != Mode::Fast) { in init()
99 if (OptMode != Mode::Fast) { in getAnalysisUsage()
647 if (OptMode == RegBankSelect::Mode::Fast) { in assignInstr()
680 OptMode = Mode::Fast; in runOnMachineFunction()
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| /llvm-project-15.0.7/llvm/test/CodeGen/ARM/ |
| H A D | fast-isel-call-multi-reg-return.ll | 5 ; Fast-isel can't handle non-double multi-reg retvals.
|
| H A D | fast-isel-vaddd.ll | 8 ; Fast-ISel was incorrectly trying to codegen <2 x double> adds and returning only a single vadds
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 1712 Align Alignment, MachineMemOperand::Flags Flags, bool *Fast) const { in allowsMemoryAccessForAlignment()
1721 if (Fast != nullptr) in allowsMemoryAccessForAlignment()
1722 *Fast = true; in allowsMemoryAccessForAlignment()
1732 const MachineMemOperand &MMO, bool *Fast) const { in allowsMemoryAccessForAlignment()
1734 MMO.getAlign(), MMO.getFlags(), Fast); in allowsMemoryAccessForAlignment()
1741 bool *Fast) const { in allowsMemoryAccess()
1743 Flags, Fast); in allowsMemoryAccess()
1749 bool *Fast) const { in allowsMemoryAccess()
1751 MMO.getFlags(), Fast); in allowsMemoryAccess()
1757 bool *Fast) const { in allowsMemoryAccess()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelLowering.h | 27 bool *Fast) const override;
|
| /llvm-project-15.0.7/llvm/unittests/Transforms/Utils/ |
| H A D | LoopUtilsTest.cpp | 80 assert(DT.verify(DominatorTree::VerificationLevel::Fast) && in TEST()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | RegBankSelect.h | 98 Fast, enumerator
620 RegBankSelect(Mode RunningMode = Fast);
|
| /llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/ |
| H A D | fast-isel-br-i1.ll | 5 ; Fast-isel uses a 32-bit xor with -1 to negate i1 values, because it doesn't
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| /llvm-project-15.0.7/llvm/lib/Target/Lanai/ |
| H A D | LanaiCallingConv.td | 30 // Lanai 32-bit Fast Calling convention.
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.h | 308 bool *Fast) const override;
313 bool *Fast) const override;
415 bool *Fast) const;
418 bool *Fast) const;
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | sgpr-regalloc-flags.ll | 28 ; O0: Fast Register Allocator
30 ; O0-NEXT: Fast Register Allocator
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | arm64-fast-isel-noconvert.ll | 3 ; Fast-isel can't do vector conversions yet, but it was emitting some highly
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsABIInfo.cpp | 52 return CC != CallingConv::Fast ? 16 : 0; in GetCalleeAllocdArgSizeInBytes()
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| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/ |
| H A D | high-reg-spill.mir | 4 # This test examines register allocation and spilling with Fast Register
|