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Searched refs:FTZ (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/NVPTX/
H A Dnvvm-intrins.ll32 ; FTZ: call float @llvm.nvvm.ceil.f
39 ; FTZ: call float @llvm.ceil.f32
53 ; FTZ: call float @llvm.nvvm.fabs.f
60 ; FTZ: call float @llvm.fabs.f32
81 ; FTZ: call float @llvm.floor.f32
102 ; FTZ: call float @llvm.fma.f32
165 ; FTZ: call float @llvm.round.f32
309 ; FTZ: fadd
330 ; FTZ: fmul
351 ; FTZ: fdiv
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Df16-instructions.ll10 ; ## Full FP16 with FTZ
14 ; RUN: | FileCheck -check-prefixes CHECK,CHECK-F16-FTZ %s
88 ; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;
104 ; CHECK-F16-FTZ-DAG: mov.b16 [[A:%h[0-9]+]], 0x3C00;
136 ; CHECK-F16-FTZ-NEXT: mov.b16 [[Z:%h[0-9]+]], 0x0000
171 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F0:%f[0-9]+]], [[A]];
172 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[F1:%f[0-9]+]], [[B]];
191 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FA:%f[0-9]+]], [[A]];
192 ; CHECK-F16-FTZ-DAG: cvt.ftz.f32.f16 [[FB:%f[0-9]+]], [[B]];
194 ; CHECK-F16-FTZ-NEXT: cvt.rzi.ftz.f32.f32 [[DI:%f[0-9]+]], [[D]];
[all …]
H A Dnvvm-reflect.ll2 ; that enables FTZ, and again with metadata that disables it.
H A Dnvvm-reflect-opaque.ll2 ; that enables FTZ, and again with metadata that disables it.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86RegisterInfo.td312 // DAZ, FTZ and exception masks. We don't model the "Defs" of flag bits.
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp537 static unsigned getPTXCmpMode(const CondCodeSDNode &CondCode, bool FTZ) { in getPTXCmpMode() argument
586 if (FTZ) in getPTXCmpMode()
H A DNVPTXInstrInfo.td1123 // frem - f32 FTZ