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Searched refs:FSRW (Results 1 – 3 of 3) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h86 FSRW, enumerator
H A DRISCVInstrInfoZb.td43 def riscv_fsrw : SDNode<"RISCVISD::FSRW", SDT_RISCVIntShiftDOpW>;
475 def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
1009 (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
H A DRISCVISelLowering.cpp6762 return RISCVISD::FSRW; in getRISCVWOpcodeByIntr()
7203 Opc = RISCVISD::FSRW; in ReplaceNodeResults()
8967 case RISCVISD::FSRW: in PerformDAGCombine()
8970 N->getOpcode() == RISCVISD::FSRW || N->getOpcode() == RISCVISD::FSLW; in PerformDAGCombine()
9676 case RISCVISD::FSRW: in ComputeNumSignBitsForTargetNode()
11631 NODE_NAME_CASE(FSRW) in getTargetNodeName()