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Searched refs:FSR (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/clang/lib/AST/
H A DPrintfFormatString.cpp418 const PrintfSpecifierResult &FSR = ParsePrintfSpecifier(H, I, E, argIndex, in ParsePrintfString() local
423 if (FSR.shouldStop()) in ParsePrintfString()
427 if (!FSR.hasValue()) in ParsePrintfString()
430 if (!H.HandlePrintfSpecifier(FSR.getValue(), FSR.getStart(), in ParsePrintfString()
431 I - FSR.getStart(), Target)) in ParsePrintfString()
453 if (FSR.shouldStop()) in ParseFormatStringHasSArg()
457 if (!FSR.hasValue()) in ParseFormatStringHasSArg()
459 const analyze_printf::PrintfSpecifier &FS = FSR.getValue(); in ParseFormatStringHasSArg()
474 const PrintfSpecifierResult &FSR = in parseFormatStringHasFormattingSpecifiers() local
476 if (FSR.shouldStop()) in parseFormatStringHasFormattingSpecifiers()
[all …]
H A DScanfFormatString.cpp549 const ScanfSpecifierResult &FSR = ParseScanfSpecifier(H, I, E, argIndex, in ParseScanfString() local
553 if (FSR.shouldStop()) in ParseScanfString()
557 if (!FSR.hasValue()) in ParseScanfString()
560 if (!H.HandleScanfSpecifier(FSR.getValue(), FSR.getStart(), in ParseScanfString()
561 I - FSR.getStart())) { in ParseScanfString()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp204 unsigned TSR, unsigned FR, unsigned FSR);
779 unsigned PredR, unsigned TR, unsigned TSR, unsigned FR, unsigned FSR) { in buildMux() argument
806 .addReg(FR, 0, FSR); in buildMux()
818 unsigned TR = 0, TSR = 0, FR = 0, FSR = 0, SR = 0, SSR = 0; in updatePhiNodes() local
826 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()
835 FR = SR, FSR = SSR; in updatePhiNodes()
844 FP.PredR, TR, TSR, FR, FSR); in updatePhiNodes()
850 MuxSR = FSR; in updatePhiNodes()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td62 def FSR : SparcCtrlReg<0, "FSR">; // Floating-point state register.
H A DSparcInstrInfo.td602 let Defs = [FSR] in {
674 let Defs = [FSR] in {
687 let rd = 1, Defs = [FSR] in {
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h82 FSR, enumerator
H A DRISCVInstrInfoZb.td45 def riscv_fsr : SDNode<"RISCVISD::FSR", SDTIntShiftDOp>;
464 def FSR : RVBTernaryR<0b10, 0b101, OPC_OP, "fsr", "$rd, $rs1, $rs3, $rs2">,
996 (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
H A DRISCVISelLowering.cpp3234 Opc = RISCVISD::FSR; in LowerOperation()
4894 return DAG.getNode(RISCVISD::FSR, DL, XLenVT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
8965 case RISCVISD::FSR: in PerformDAGCombine()
11633 NODE_NAME_CASE(FSR) in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp1124 case Sparc::FSR: in parseSparcAsmOperand()
1260 RegNo = Sparc::FSR; in matchRegisterName()