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Searched refs:FSEL (Results 1 – 6 of 6) sorted by relevance

/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dscalable-reduction-inloop-cond.ll147 ; CHECK-NEXT: [[FSEL:%.*]] = select fast i1 [[FCMP]], float [[RDX]], float [[TMP18]]
150 ; CHECK-NEXT: [[RES]] = phi float [ [[RDX]], [[FOR_BODY]] ], [ [[FSEL]], [[IF_THEN]] ]
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DREADME.txt548 ; This could generate FSEL with appropriate flags (FSEL is not IEEE-safe, and
H A DPPCISelLowering.h52 FSEL, enumerator
H A DPPCISelLowering.cpp1610 case PPCISD::FSEL: return "PPCISD::FSEL"; in getTargetNodeName()
7952 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7955 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7965 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); in LowerSELECT_CC()
7974 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7988 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
7991 return DAG.getNode(PPCISD::FSEL, dl, ResVT, in LowerSELECT_CC()
7998 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
8004 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); in LowerSELECT_CC()
8010 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); in LowerSELECT_CC()
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H A DP9InstrResources.td457 (instregex "FSEL(D|S)_rec$")
H A DPPCInstrInfo.td197 def PPCfsel : SDNode<"PPCISD::FSEL",
2859 // FSEL is artificially split into 4 and 8-byte forms for the result. To avoid