Searched refs:FReg (Results 1 – 7 of 7) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | EarlyIfConversion.cpp | 113 unsigned TReg = 0, FReg = 0; member
517 PI.FReg = PI.PHI->getOperand(i).getReg(); in canConvertIf()
561 Register FReg) { in hasSameValue() argument
562 if (TReg == FReg) in hasSameValue()
565 if (!TReg.isVirtual() || !FReg.isVirtual()) in hasSameValue()
569 const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg); in hasSameValue()
597 int FIdx = FDef->findRegisterDefOperandIdx(FReg); in hasSameValue()
618 if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) { in replacePHIInstrs()
625 PI.FReg); in replacePHIInstrs()
647 if (hasSameValue(*MRI, TII, PI.TReg, PI.FReg)) { in rewritePHIOperands()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVAsmPrinter.cpp | 402 Register FReg = MAI->getFuncReg(F.getGlobalIdentifier()); in outputExecutionMode() local
403 assert(FReg.isValid()); in outputExecutionMode()
405 outputExecutionModeFromMDNode(FReg, Node, in outputExecutionMode()
408 outputExecutionModeFromMDNode(FReg, Node, in outputExecutionMode()
411 outputExecutionModeFromMDNode(FReg, Node, in outputExecutionMode()
416 Inst.addOperand(MCOperand::createReg(FReg)); in outputExecutionMode()
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| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 902 unsigned FReg = StringSwitch<unsigned>(Constraint.lower()) in getRegForInlineAsmConstraint() local
936 if (FReg != CSKY::NoRegister) { in getRegForInlineAsmConstraint()
937 assert(CSKY::F0_32 <= FReg && FReg <= CSKY::F31_32 && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
938 unsigned RegNo = FReg - CSKY::F0_32; in getRegForInlineAsmConstraint()
946 return std::make_pair(FReg, &CSKY::sFPR32RegClass); in getRegForInlineAsmConstraint()
948 return std::make_pair(FReg, &CSKY::FPR32RegClass); in getRegForInlineAsmConstraint()
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| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 594 Register FReg = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass); in insertSelect() local
596 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
598 FalseReg = FReg; in insertSelect()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11873 unsigned FReg = StringSwitch<unsigned>(Constraint.lower()) in getRegForInlineAsmConstraint() local
11907 if (FReg != RISCV::NoRegister) { in getRegForInlineAsmConstraint()
11908 assert(RISCV::F0_F <= FReg && FReg <= RISCV::F31_F && "Unknown fp-reg"); in getRegForInlineAsmConstraint()
11910 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
11915 return std::make_pair(FReg, &RISCV::FPR32RegClass); in getRegForInlineAsmConstraint()
11917 unsigned RegNo = FReg - RISCV::F0_F; in getRegForInlineAsmConstraint()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 3346 const Register FReg = Sel.getFalseReg(); in select() local
3357 if (!emitSelect(Sel.getReg(0), TReg, FReg, AArch64CC::NE, MIB)) in select()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 6672 unsigned FReg = State.AllocateReg(FPR); in CC_AIX() local
6673 if (FReg) in CC_AIX()
6674 State.addLoc(CCValAssign::getReg(ValNo, ValVT, FReg, LocVT, LocInfo)); in CC_AIX()
6679 assert(FReg && "An FPR should be available when a GPR is reserved."); in CC_AIX()
6696 FReg ? CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, in CC_AIX()
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