| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | fract.f64.ll | 12 ; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
15 ; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]
39 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
42 ; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]
67 ; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
70 ; SI-DAG: v_min_f64 v[[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], [[FRC]], v[[[UPLO]]:[[UPHI]]]
|
| /llvm-project-15.0.7/clang/test/Profile/ |
| H A D | objc-general.m | 36 // PGOGEN: @[[FRC:"__profc_objc_general.m_\+\[A foreach_\]"]] = private global [2 x i64] zeroinitia…
47 // PGOGEN: store {{.*}} @[[FRC]], i32 0, i32 0
51 // PGOGEN: store {{.*}} @[[FRC]], i32 0, i32 1
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitSimplify.cpp | 1374 Register NewR = MRI.createVirtualRegister(FRC); in processBlock()
1578 auto *FRC = HBS::getFinalVRegClass(Inp, MRI); in findMatch() local
1589 if (FRC != MRI.getRegClass(R)) in findMatch()
1642 auto *FRC = HBS::getFinalVRegClass(R, MRI); in processBlock() local
1654 if (FRC == &Hexagon::DoubleRegsRegClass || in processBlock()
1655 FRC == &Hexagon::HvxWRRegClass) { in processBlock()
1663 auto *FRC = HBS::getFinalVRegClass(R, MRI); in processBlock() local
2439 if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass) in simplifyExtractLow()
2577 Register NewR = MRI.createVirtualRegister(FRC); in simplifyExtractLow()
2621 if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass) in simplifyRCmp0()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX512.td | 5572 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
5619 [(set _.FRC:$dst, (OpNode _.FRC:$src1, _.FRC:$src2))]>,
7065 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3),
7077 (ins _.FRC:$src1, _.FRC:$src2, _.FRC:$src3, AVX512RC:$rc),
7093 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
7095 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
7097 (set _.FRC:$dst, (_.EltVT (OpNodeRnd _.FRC:$src2, _.FRC:$src1,
7101 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
7105 (set _.FRC:$dst, (_.EltVT (OpNodeRnd _.FRC:$src2, _.FRC:$src3,
7111 (set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.td | 2821 "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2829 "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2839 "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2849 "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
2866 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2870 "fsel", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
2893 (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC),
2894 "fmul", "$FRT, $FRA, $FRC", IIC_FPFused,
2897 (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC),
2898 "fmuls", "$FRT, $FRA, $FRC", IIC_FPGeneral,
[all …]
|
| H A D | PPCInstrFormats.td | 1768 bits<5> FRC;
1778 let Inst{21-25} = FRC;
1786 let FRC = 0;
|
| /llvm-project-15.0.7/llvm/unittests/Analysis/ |
| H A D | LazyCallGraphTest.cpp | 1973 LazyCallGraph::RefSCC &FRC = *I++; in TEST() local
1979 EXPECT_EQ(&FRC, CG.lookupRefSCC(F)); in TEST()
1981 EXPECT_FALSE(GRC.isParentOf(FRC)); in TEST()
1982 EXPECT_FALSE(FRC.isParentOf(GRC)); in TEST()
2002 LazyCallGraph::RefSCC &FRC = *I++; in TEST() local
2008 EXPECT_EQ(&FRC, CG.lookupRefSCC(F)); in TEST()
2010 EXPECT_FALSE(GRC.isParentOf(FRC)); in TEST()
2011 EXPECT_FALSE(FRC.isParentOf(GRC)); in TEST()
|
| /llvm-project-15.0.7/llvm/docs/ |
| H A D | CodeGenerator.rst | 1052 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1053 "fmadds $FRT, $FRA, $FRC, $FRB",
1054 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
|