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Searched refs:FPR8 (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp315 const auto &FPR8 = AArch64MCRegisterClasses[AArch64::FPR8RegClassID]; in isFpOrNEON() local
322 FPR16.contains(Reg) || FPR8.contains(Reg); in isFpOrNEON()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td433 def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> {
660 def FPR8Op : RegisterOperand<FPR8, "printOperand"> {
661 let ParserMatchClass = FPRAsmOperand<"FPR8">;
H A DAArch64InstrFormats.td6914 def v1i8 : BaseSIMDThreeScalar<U, 0b001, opc, FPR8 , asm, []>;
7177 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR8 , asm, []>;
7192 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
7207 def v1i8 : BaseSIMDTwoScalar<U, 0b00, 0b00, opc, FPR8 , FPR16, asm, []>;
7278 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
7280 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
7797 def i8 : BaseSIMDScalarDUP<FPR8, V128, asm, ".b", VectorIndexB> {
7825 FPR8, V128, VectorIndexB>;
9162 FPR8, FPR16, vecshiftR8, asm, []> {
9181 FPR8, FPR8, vecshiftL8, asm, []> {
[all …]
H A DSVEInstrFormats.td6397 def _B : sve_int_perm_clast_vz<0b00, ab, asm, ZPR8, FPR8>;
6501 def _B : sve_int_perm_last_v<0b00, ab, asm, ZPR8, FPR8>;
6703 def _B : sve_int_perm_cpy_v<0b00, asm, ZPR8, FPR8>;
6709 (!cast<Instruction>(NAME # _B) ZPR8:$Zd, PPR3bAny:$Pg, FPR8:$Vn), 1>;