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Searched refs:FPR64 (Results 1 – 25 of 25) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td80 def FFINT_D_L : FP_CONV<0b0000000100011101001010, "ffint.d.l", FPR64, FPR64>;
82 def FTINT_L_D : FP_CONV<0b0000000100011011001010, "ftint.l.d", FPR64, FPR64>;
84 FPR64>;
99 def FRINT_D : FP_CONV<0b0000000100011110010010, "frint.d", FPR64, FPR64>;
102 def FMOV_D : FP_MOV<0b0000000100010100100110, "fmov.d", FPR64, FPR64>;
178 def : Pat<(select GPR:$cc, FPR64:$fk, FPR64:$fj),
179 (FSEL_D FPR64:$fj, FPR64:$fk, (MOVGR2CF GPR:$cc))>;
204 def : Pat<(loongarch_ftint FPR64:$src), (FTINTRZ_W_D FPR64:$src)>;
205 def : Pat<(f64 (loongarch_ftint FPR64:$src)), (FTINTRZ_L_D FPR64:$src)>;
209 def : Pat<(f32 (fpround FPR64:$src)), (FCVT_S_D FPR64:$src)>;
[all …]
H A DLoongArchRegisterInfo.td144 def FPR64 : RegisterClass<"LoongArch", [f64], 64, (sequence "F%u_64", 0, 31)>;
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td209 def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
210 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
282 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
286 def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
287 (FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
290 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
291 (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
294 def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
295 (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
298 def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
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H A DRISCVInstrInfoZfh.td70 def DHmin : ExtInfo_rr<ZfhminDExt, FPR64, FPR16>;
72 def HDmin : ExtInfo_rr<ZfhminDExt, FPR16, FPR64>;
416 def : Pat<(any_fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, 0b111)>;
420 def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
422 def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
H A DRISCVInstrInfoC.td489 def C_FLDSP : CStackLoad<0b001, "c.fldsp", FPR64, uimm9_lsb000>,
549 def C_FSDSP : CStackStore<0b101, "c.fsdsp", FPR64, uimm9_lsb000>,
859 def : CompressPat<(FLD FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm),
860 (C_FLDSP FPR64:$rd, SP:$rs1, uimm9_lsb000:$imm)>;
901 def : CompressPat<(FSD FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm),
902 (C_FSDSP FPR64:$rs2, SP:$rs1, uimm9_lsb000:$imm)>;
H A DRISCVRegisterInfo.td251 def FPR64 : RegisterClass<"RISCV", [f64], 64, (add
H A DRISCVInstrInfoVPseudos.td130 def SCALAR_F64 : FPR_Info<FPR64, "F64", MxSet<64>.m>;
253 def VF64M1: VTypeInfo<vfloat64m1_t, vbool64_t, 64, VR, V_M1, f64, FPR64>;
272 VRM2, V_M2, f64, FPR64>;
274 VRM4, V_M4, f64, FPR64>;
276 VRM8, V_M8, f64, FPR64>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td4173 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
4174 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
4185 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
4186 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
4925 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
4927 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
4929 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
4935 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
4939 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
4943 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
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H A DAArch64InstrFormats.td5136 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
5182 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
6905 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6911 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
6916 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
6944 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
6962 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
7138 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
7188 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
8442 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
[all …]
H A DAArch64RegisterInfo.td444 def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
450 64, (trunc FPR64, 16)>;
468 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
470 [(rotl FPR64, 0), (rotl FPR64, 1),
471 (rotl FPR64, 2)]>;
473 [(rotl FPR64, 0), (rotl FPR64, 1),
474 (rotl FPR64, 2), (rotl FPR64, 3)]>;
515 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
648 defm VecListOne : VectorList<1, FPR64, FPR128>;
676 def FPR64Op : RegisterOperand<FPR64, "printOperand"> {
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H A DAArch64InstrGISel.td245 def : Pat<(f32 (fadd (vector_extract (v2f32 FPR64:$Rn), (i64 0)),
246 (vector_extract (v2f32 FPR64:$Rn), (i64 1)))),
247 (f32 (FADDPv2i32p (v2f32 FPR64:$Rn)))>;
H A DAArch64FrameLowering.cpp2483 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
2494 case FPR64: in getScale()
2553 RPI.Type = RegPairInfo::FPR64; in computeCalleeSaveRegisterPairs()
2574 case RegPairInfo::FPR64: in computeCalleeSaveRegisterPairs()
2750 case RegPairInfo::FPR64: in spillCalleeSavedRegisters()
2854 case RegPairInfo::FPR64: in restoreCalleeSavedRegisters()
H A DAArch64SVEInstrInfo.td702 def : Pat<(nxv2f64 (splat_vector (f64 FPR64:$src))),
703 (DUP_ZZI_D (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), 0)>;
2852 def : Pat<(nxv2i64 (vector_insert (nxv2i64 (undef)), (i64 FPR64:$src), 0)),
2853 (INSERT_SUBREG (nxv2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
2865 def : Pat<(nxv2f64 (vector_insert (nxv2f64 (undef)), (f64 FPR64:$src), 0)),
2866 (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
2882 def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), 0)),
2883 (SEL_ZPZZ_D (PTRUE_D 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), ZPR:$vec)>;
2942 def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), GPR64:$index)),
H A DSVEInstrFormats.td6400 def _D : sve_int_perm_clast_vz<0b11, ab, asm, ZPR64, FPR64>;
6504 def _D : sve_int_perm_last_v<0b11, ab, asm, ZPR64, FPR64>;
6706 def _D : sve_int_perm_cpy_v<0b11, asm, ZPR64, FPR64>;
6715 (!cast<Instruction>(NAME # _D) ZPR64:$Zd, PPR3bAny:$Pg, FPR64:$Vn), 1>;
/llvm-project-15.0.7/llvm/test/TableGen/
H A Dambiguous-composition.td46 class FPR64<string n, FPR32 high> : TestReg<n, [high]> {
50 class FPR128<string n, FPR64 high, FPR32 low> : TestReg<n, [high, low]> {
54 class VPR128<string n, FPR64 high> : TestReg<n, [high]> {
62 def F0D : FPR64<"f0d", F0S>;
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfp16-vector-nvcast.ll3 ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src)))
14 ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src)))
25 ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src)))
36 ; Test pattern (v4f16 (AArch64NvCast (f64 FPR64:$src)))
H A Daarch64-vector-pcs.mir7 # the stack pointer after the GPR64/FPR64 block (which is also needed
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td210 class FPR64<bits<16> num, string n, FPR32 high>
217 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
227 def F#I#D : FPR64<I, "f"#I, !cast<FPR32>("F"#I#"S")>,
232 def F#I#D : FPR64<I, "v"#I, !cast<FPR32>("F"#I#"S")>,
237 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
238 !cast<FPR64>("F"#I#"D")>;
252 // A full 128-bit vector register, with an FPR64 as its high part.
253 class VR128<bits<16> num, string n, FPR64 high>
261 def V#I : VR128<I, "v"#I, !cast<FPR64>("F"#I#"D")>,
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dregbank-inlineasm.mir78 …0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1376266 /* regdef:FPR64 */, def %1
83 …t */, 655370 /* regdef:GPR32common */, def %0:gpr32common, 1376266 /* regdef:FPR64 */, def %1:fpr64
H A Dselect-neon-vcvtfxu2fp.mir11 # Check that we select a 64-bit FPR vcvtfxu2fp intrinsic into UCVTFd for FPR64.
H A Dirtranslator-inline-asm.ll99 …0", 0 /* attdialect */, 655370 /* regdef:GPR32common */, def %0, 1376266 /* regdef:FPR64 */, def %1
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Ddouble-mem.ll125 %4 = fadd double %3, %a ; force load in to FPR64
153 %1 = fadd double %a, %b ; force store from FPR64
/llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.cpp312 const auto &FPR64 = AArch64MCRegisterClasses[AArch64::FPR64RegClassID]; in isFpOrNEON() local
321 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td196 def FPR64 : RegisterClass<"CSKY", [f64], 32,
H A DCSKYInstrInfoF2.td26 let MIOperandInfo = (ops FPR64, uimm5);
30 def FPR64Op : RegisterOperand<FPR64, "printFPR">;