| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 4212 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
4214 (AArch64csel FPR128:$Rn, FPR128:$Rm,
5060 (FRECPSv4f32 FPR128:$Rn, FPR128:$Rm)>;
5064 (FRECPSv2f64 FPR128:$Rn, FPR128:$Rm)>;
5100 (FRSQRTSv4f32 FPR128:$Rn, FPR128:$Rm)>;
5104 (FRSQRTSv2f64 FPR128:$Rn, FPR128:$Rm)>;
7780 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
7781 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
7782 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
7783 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
[all …]
|
| H A D | AArch64RegisterInfo.td | 455 def FPR128 : RegisterClass<"AArch64",
465 128, (trunc FPR128, 16)>;
486 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
488 [(rotl FPR128, 0), (rotl FPR128, 1),
489 (rotl FPR128, 2)]>;
491 [(rotl FPR128, 0), (rotl FPR128, 1),
492 (rotl FPR128, 2), (rotl FPR128, 3)]>;
519 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
648 defm VecListOne : VectorList<1, FPR64, FPR128>;
680 def FPR128Op : RegisterOperand<FPR128, "printOperand"> {
[all …]
|
| H A D | AArch64FrameLowering.cpp | 2483 enum RegType { GPR, FPR64, FPR128, PPR, ZPR } Type; enumerator
2497 case FPR128: in getScale()
2555 RPI.Type = RegPairInfo::FPR128; in computeCalleeSaveRegisterPairs()
2580 case RegPairInfo::FPR128: in computeCalleeSaveRegisterPairs()
2645 !RPI.isScalable() && RPI.Type != RegPairInfo::FPR128 && in computeCalleeSaveRegisterPairs()
2755 case RegPairInfo::FPR128: in spillCalleeSavedRegisters()
2859 case RegPairInfo::FPR128: in restoreCalleeSavedRegisters()
|
| H A D | AArch64InstrFormats.td | 11003 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
11004 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
11005 [(set (v4i32 FPR128:$dst),
11006 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
11017 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
11018 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
11019 [(set (v4i32 FPR128:$dst),
11020 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
11099 : CryptoRRR<op0, op1, (outs FPR128:$Vdst), (ins FPR128:$Vd, FPR128:$Vn, V128:$Vm),
|
| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | fp16-vector-nvcast.ll | 46 ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src)))
57 ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src)))
68 ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src)))
79 ; Test pattern (v8f16 (AArch64NvCast (v2i64 FPR128:$src)))
|
| H A D | aarch64-vector-pcs.mir | 8 # for the FPR128 saves when present).
12 # FPR128 saves. The alignment can leave a gap that can be scavenged
|
| /llvm-project-15.0.7/llvm/test/TableGen/ |
| H A D | ambiguous-composition.td | 50 class FPR128<string n, FPR64 high, FPR32 low> : TestReg<n, [high, low]> {
63 def F0Q : FPR128<"f0q", F0D, F2S>;
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64MCTargetDesc.cpp | 304 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; in isQForm() local
306 return Op.isReg() && FPR128.contains(Op.getReg()); in isQForm()
311 const auto &FPR128 = AArch64MCRegisterClasses[AArch64::FPR128RegClassID]; in isFpOrNEON() local
321 return FPR128.contains(Reg) || FPR64.contains(Reg) || FPR32.contains(Reg) || in isFpOrNEON()
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.td | 217 class FPR128<bits<16> num, string n, FPR64 low, FPR64 high>
237 def F#I#Q : FPR128<I, "f"#I, !cast<FPR64>("F"#!add(I, 2)#"D"),
|
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.td | 203 def FPR128 : RegisterClass<"CSKY",
|