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Searched refs:FPCR (Results 1 – 9 of 9) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dfpenv.ll10 ; CHECK: mrs x8, FPCR
15 ; CHECK: msr FPCR, x8
25 ; CHECK: mrs x8, FPCR
27 ; CHECK: msr FPCR, x8
37 ; CHECK: mrs x8, FPCR
39 ; CHECK: msr FPCR, x8
50 ; CHECK: mrs x8, FPCR
53 ; CHECK: msr FPCR, x8
63 ; CHECK: mrs x8, FPCR
66 ; CHECK: msr FPCR, x8
H A Darm64-fpcr.ll5 ; CHECK: mrs x0, FPCR
15 ; CHECK: mrs x8, FPCR
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dbasic-a64-instructions.s3813 msr FPCR, x12
4361 mrs x9, FPCR
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4323 SDValue FPCR = in LowerSET_ROUNDING() local
4325 Chain = FPCR.getValue(1); in LowerSET_ROUNDING()
4326 FPCR = FPCR.getValue(0); in LowerSET_ROUNDING()
4330 FPCR = DAG.getNode(ISD::AND, DL, MVT::i64, FPCR, in LowerSET_ROUNDING()
4332 FPCR = DAG.getNode(ISD::OR, DL, MVT::i64, FPCR, RMValue); in LowerSET_ROUNDING()
4335 FPCR}; in LowerSET_ROUNDING()
H A DAArch64SystemOperands.td949 def : RWSysReg<"FPCR", 0b11, 0b011, 0b0100, 0b0100, 0b000>;
H A DAArch64InstrInfo.td1467 // FPCR register
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td706 // FPCR
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-instructions.txt3287 # CHECK: msr {{fpcr|FPCR}}, x12
3582 # CHECK: mrs x9, {{fpcr|FPCR}}
/llvm-project-15.0.7/clang/unittests/Format/
H A DFormatTest.cpp23402 asm volatile("mrs %x[result], FPCR" : [result] "=r"(result)); in TEST_F()