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Searched refs:FNMSUB (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp1493 case CASE_VFMA_SPLATS(FNMSUB): in findCommutedOpIndices()
1523 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV): in findCommutedOpIndices()
1640 case CASE_VFMA_SPLATS(FNMSUB): in commuteInstructionImpl()
1665 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSAC, FNMSUB) in commuteInstructionImpl()
1666 CASE_VFMA_CHANGE_OPCODE_SPLATS(FNMSUB, FNMSAC) in commuteInstructionImpl()
1670 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMSAC, FNMSUB, VV) in commuteInstructionImpl()
1687 case CASE_VFMA_OPCODE_LMULS_MF4(FNMSUB, VV): in commuteInstructionImpl()
1701 CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(FNMSUB, FNMSAC, VV) in commuteInstructionImpl()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCSchedPredicates.td59 FNMSUB,
H A DPPCISelLowering.h170 FNMSUB, enumerator
H A DP10InstrResources.td210 FNMSUB,
H A DP9InstrResources.td426 FNMSUB,
H A DPPCISelLowering.cpp1754 case PPCISD::FNMSUB: return "PPCISD::FNMSUB"; in getTargetNodeName()
10571 return DAG.getNode(PPCISD::FNMSUB, dl, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
15117 case PPCISD::FNMSUB: in PerformDAGCombine()
16848 return PPCISD::FNMSUB; in invertFMAOpcode()
16849 case PPCISD::FNMSUB: in invertFMAOpcode()
16866 case PPCISD::FNMSUB: in getNegatedExpression()
H A DPPCInstrInfo.td248 def PPCfnmsub : SDNode<"PPCISD::FNMSUB" , SDTFPTernaryOp>;
2847 defm FNMSUB : AForm_1r<63, 30,
3225 (FNMSUB $A, $B, $C)>;
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp359 CASE_FMA4_PACKED_RR(FNMSUB) in printFMAComments()
360 CASE_FMA4_SCALAR_RR(FNMSUB) in printFMAComments()
363 CASE_FMA4_PACKED_RM(FNMSUB) in printFMAComments()
364 CASE_FMA4_SCALAR_RM(FNMSUB) in printFMAComments()
370 CASE_FMA4_PACKED_MR(FNMSUB) in printFMAComments()
371 CASE_FMA4_SCALAR_MR(FNMSUB) in printFMAComments()
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Cortex/
H A Dforwarding-A57.s318 # FMUL, FMUL, FNMUL, FMADD, FMSUB, FNMADD, FNMSUB are impacted
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.h554 FNMSUB, enumerator
H A DX86InstrFragmentsSIMD.td550 def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFPTernaryOp, [SDNPCommutative]>;
H A DX86ISelLowering.cpp33673 NODE_NAME_CASE(FNMSUB) in getTargetNodeName()
50692 case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
50698 case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break; in negateFMAOpcode()
50713 case X86ISD::FNMADD: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
50716 case X86ISD::FNMSUB: Opcode = X86ISD::FNMADD; break; in negateFMAOpcode()
50730 case ISD::FMA: Opcode = X86ISD::FNMSUB; break; in negateFMAOpcode()
50736 case X86ISD::FNMSUB: Opcode = ISD::FMA; break; in negateFMAOpcode()
50768 SDValue NewNode = DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0), in combineFneg()
50801 case X86ISD::FNMSUB: in getNegatedExpression()
55172 case X86ISD::FNMSUB: in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td1184 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64SchedThunderX3T110.td1291 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64SchedA64FX.td1559 (instregex "^FMADD", "^FMSUB", "^FNMADD", "^FNMSUB")>;
H A DAArch64InstrInfo.td4155 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",