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Searched refs:FNEG (Results 1 – 25 of 76) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dcombine-foldable-fneg.mir16 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
580 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
601 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
623 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
646 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
669 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
692 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
738 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
758 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
784 ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32)
[all …]
H A Dlegalize-fneg.mir18 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
19 ; SI-NEXT: $vgpr0 = COPY [[FNEG]](s32)
24 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
25 ; VI-NEXT: $vgpr0 = COPY [[FNEG]](s32)
31 ; GFX9-NEXT: $vgpr0 = COPY [[FNEG]](s32)
47 ; SI-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
53 ; VI-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
59 ; GFX9-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64)
229 ; SI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>)
235 ; VI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>)
[all …]
H A Dregbankselect-fneg.mir16 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:sgpr(s32) = G_FNEG [[COPY]]
17 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
34 ; CHECK-NEXT: [[FNEG:%[0-9]+]]:vgpr(s32) = G_FNEG [[COPY]]
35 ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32)
H A Dlegalize-fdiv.mir35 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
134 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
153 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
172 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
237 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
258 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
279 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
457 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]]
483 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[INT]]
579 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]]
[all …]
H A Dinst-select-fneg.mir117 ; GCN: $vgpr0 = COPY [[FNEG]](s32)
123 ; SI-NEXT: $vgpr0 = COPY [[FNEG]](s32)
129 ; VI-NEXT: $vgpr0 = COPY [[FNEG]](s32)
135 ; GFX9-NEXT: $vgpr0 = COPY [[FNEG]](s32)
141 ; GFX10-NEXT: $vgpr0 = COPY [[FNEG]](s32)
412 ; GCN: $vgpr0 = COPY [[FNEG]](<2 x s16>)
418 ; SI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>)
424 ; VI-NEXT: $vgpr0 = COPY [[FNEG]](<2 x s16>)
581 ; GCN: S_ENDPGM 0, implicit [[FNEG]](s64)
587 ; SI-NEXT: S_ENDPGM 0, implicit [[FNEG]](s64)
[all …]
H A Dlegalize-fsub.mir51 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
59 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
67 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
87 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
95 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
103 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
125 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC1]]
313 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[UV2]]
326 ; VI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[UV2]]
339 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[UV2]]
[all …]
H A Dinst-select-ffloor.s16.mir89 ; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
90 ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
H A Dinst-select-fmul.v2s16.mir68 ; GFX9-NEXT: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
69 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16)
H A Dlegalize-frint.mir76 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
77 ; SI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
192 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[OR]]
193 ; SI-NEXT: [[FADD1:%[0-9]+]]:_(s64) = G_FADD [[FADD]], [[FNEG]]
H A Dlegalize-intrinsic-round.mir162 ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT1]]
163 ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
339 ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT1]]
340 ; GFX6-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
380 ; GFX8-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
409 ; GFX9-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
450 ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
452 ; GFX6-NEXT: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16)
535 ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
673 ; GFX6-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FPTRUNC]]
[all …]
H A Dlegalize-ffloor.mir52 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT]]
53 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
86 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
87 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[COPY]], [[FNEG]]
122 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = nsz G_FNEG [[SELECT]]
123 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nsz G_FADD [[COPY]], [[FNEG]]
277 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT]]
278 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[UV]], [[FNEG]]
H A Dcombine-fma-unmerge-values.mir396 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG %el1
397 ; GFX10-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[FNEG]]
426 ; GFX10-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]]
427 ; GFX10-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FNEG]], [[COPY1]], %el1
H A Dlegalize-fptoui.mir224 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT2]]
225 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[FNEG]]
286 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = nnan G_FNEG [[FMINNUM_IEEE]]
287 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = nnan G_FADD [[FMUL]], [[FNEG]]
351 ; SI-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[SELECT2]]
352 ; SI-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[FMUL]], [[FNEG]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dreduction2.ll89 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]]
92 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> [[TMP0]], double [[FNEG]], i32 0
138 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[B:%.*]]
141 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[FNEG]], i32 0
H A Dc-ray.ll48 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[TMP6]]
51 ; CHECK-NEXT: [[TMP19:%.*]] = tail call double @llvm.fmuladd.f64(double [[FNEG]], double [[TMP5]…
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp3554 (LHS.getOpcode() == ISD::FNEG && RHS.getOpcode() == ISD::FNEG)) { in foldFreeOpFromSelect()
3586 if (LHS.getOpcode() == ISD::FNEG) in foldFreeOpFromSelect()
3727 if (LHS.getOpcode() != ISD::FNEG) in performFNegCombine()
3732 if (RHS.getOpcode() != ISD::FNEG) in performFNegCombine()
3751 if (LHS.getOpcode() == ISD::FNEG) in performFNegCombine()
3753 else if (RHS.getOpcode() == ISD::FNEG) in performFNegCombine()
3776 if (LHS.getOpcode() == ISD::FNEG) in performFNegCombine()
3778 else if (MHS.getOpcode() == ISD::FNEG) in performFNegCombine()
3783 if (RHS.getOpcode() != ISD::FNEG) in performFNegCombine()
3855 if (CvtSrc.getOpcode() == ISD::FNEG) { in performFNegCombine()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-fp-arith.mir54 ; CHECK: [[FNEG:%[0-9]+]]:_(<2 x s32>) = G_FNEG [[COPY]]
55 ; CHECK: $d0 = COPY [[FNEG]](<2 x s32>)
H A Dlegalize-fp-arith-fp16.mir141 ; NO-FP16: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FPEXT]]
142 ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FNEG]](s32)
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dunroll_nonlatch.ll51 ; CHECK-NEXT: [[FNEG:%.*]] = fneg double [[T17]]
52 ; CHECK-NEXT: store double [[FNEG]], double* [[ARRAYIDX]], align 8
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-fneg.ll74 ; CHECK-NEXT: [[FNEG:%.*]] = fneg half [[TMP24]]
76 ; CHECK-NEXT: store half [[FNEG]], ptr [[ARRAYIDX2]], align 2
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dlegalize-fneg.ll7 ; Check Y = FNEG(X) -> Y = X ^ sign mask and no lib call is generated.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfnabs.ll4 ; FNABS(x) operation -> FNEG (FABS(x)).
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def111 ADD_UNARY_VVP_OP(VVP_FNEG, FNEG) HANDLE_VP_TO_VVP(VP_FNEG, VVP_FNEG) REGISTER_PACKED(VVP_FNEG)
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dfcmp.ll926 ; CHECK-NEXT: [[FNEG:%.*]] = fneg float [[A:%.*]]
927 ; CHECK-NEXT: store float [[FNEG]], float* [[Q:%.*]], align 4
999 ; CHECK-NEXT: [[FNEG:%.*]] = fneg float [[A:%.*]]
1000 ; CHECK-NEXT: store float [[FNEG]], float* [[Q:%.*]], align 4
1079 ; CHECK-NEXT: [[FNEG:%.*]] = fneg float [[A]]
1080 ; CHECK-NEXT: store float [[FNEG]], float* [[Q:%.*]], align 4
1166 ; CHECK-NEXT: [[FNEG:%.*]] = fneg float [[A]]
1167 ; CHECK-NEXT: store float [[FNEG]], float* [[Q:%.*]], align 4
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h911 FNEG, enumerator

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