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Searched refs:FMAX (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/test/TableGen/
H A DDefaultOpsGlobalISel.td37 // CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
58 // CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::FMAX,
178 def FMAX : I<(outs FPR32:$dst),
186 (FMAX $mods, $src, $mods, $src, 0)
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dpr45709.ll6 ; There is code in the SDAG to expand FMAX/FMIN with fast flags to SELECT_CC.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h357 X86_INTRINSIC_DATA(avx_max_pd_256, INTR_TYPE_2OP, X86ISD::FMAX, 0),
358 X86_INTRINSIC_DATA(avx_max_ps_256, INTR_TYPE_2OP, X86ISD::FMAX, 0),
812 X86_INTRINSIC_DATA(avx512_max_pd_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
813 X86_INTRINSIC_DATA(avx512_max_ps_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
1189 X86_INTRINSIC_DATA(avx512fp16_max_ph_128, INTR_TYPE_2OP, X86ISD::FMAX, 0),
1190 X86_INTRINSIC_DATA(avx512fp16_max_ph_256, INTR_TYPE_2OP, X86ISD::FMAX, 0),
1191 X86_INTRINSIC_DATA(avx512fp16_max_ph_512, INTR_TYPE_2OP_SAE, X86ISD::FMAX, X86ISD::FMAX_SAE),
1246 X86_INTRINSIC_DATA(sse_max_ps, INTR_TYPE_2OP, X86ISD::FMAX, 0),
1277 X86_INTRINSIC_DATA(sse2_max_pd, INTR_TYPE_2OP, X86ISD::FMAX, 0),
H A DX86ISelLowering.h264 FMAX, enumerator
H A DX86InstrFragmentsSIMD.td39 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
43 // Commutative and Associative FMIN and FMAX.
H A DX86ISelLowering.cpp22823 X86ISD::FMAX, dl, SrcVT, Src, MinFloatNode); in LowerFP_TO_INT_SAT()
32513 case X86ISD::FMAX: { in ReplaceNodeResults()
33502 NODE_NAME_CASE(FMAX) in getTargetNodeName()
33921 case X86ISD::FMAX: in isBinOp()
43667 case X86ISD::FMAX: in scalarizeExtEltFP()
44654 Opcode = X86ISD::FMAX; in combineSelect()
44667 Opcode = X86ISD::FMAX; in combineSelect()
44677 Opcode = X86ISD::FMAX; in combineSelect()
44719 Opcode = X86ISD::FMAX; in combineSelect()
44732 Opcode = X86ISD::FMAX; in combineSelect()
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/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedA57.td483 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?(v2f32)")>;
485 def : InstRW<[A57Write_5cyc_2V], (instregex "^(FMAX|FMIN)(NM)?(v4f32|v2f64)")>;
487 def : InstRW<[A57Write_5cyc_1V], (instregex "^(FMAX|FMIN)(NM)?P(v2f32|v2i32)")>;
489 def : InstRW<[A57Write_9cyc_3V], (instregex "^(FMAX|FMIN)(NM)?P(v4f32|v2f64|v2i64)")>;
491 def : InstRW<[A57Write_10cyc_3V], (instregex "^(FMAX|FMIN)(NM)?Vv")>;
H A DAArch64SchedNeoverseN2.td1083 def : InstRW<[N2Write_4cyc_1V], (instregex "^(FMAX|FMIN)(NM)?Vv4(i16|i32)v$")>;
1086 def : InstRW<[N2Write_6cyc_2V], (instregex "^(FMAX|FMIN)(NM)?Vv8i16v$")>;
H A DAArch64InstrInfo.td4128 defm FMAX : TwoOperandFPData<0b0100, "fmax", any_fmaximum>;
4584 defm FMAX : SIMDThreeSameVectorFP<0,0,0b110,"fmax", any_fmaximum>;
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dscalable-reductions.ll288 ; FMAX (FAST)
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dscalable-reductions.ll291 ; FMAX (FAST)
/llvm-project-15.0.7/llvm/docs/GlobalISel/
H A DGenericOpcode.rst653 FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dexpand-vp.ll217 ; ALL-CONVERT: [[FMAX:%.+]] = select <4 x i1> %{{.+}}, <4 x float> %vf, <4 x float> <float 0xFFF80…
218 ; ALL-CONVERT-NEXT: [[RED:%.+]] = call float @llvm.vector.reduce.fmax.v4f32(<4 x float> [[FMAX]])
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-intrinsics-fp-arith-merging.ll48 ; FMAX
H A Dsve-fixed-length-fp-minmax.ll605 ; FMAX
H A Dsve-fp-immediates-merging.ll156 ; FMAX
H A Dsve-intrinsics-fp-arith.ll374 ; FMAX
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVVLPatterns.td296 "FADD", "SEQ_FADD", "FMIN", "FMAX"] in
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td915 defm FMAX : F3<"max", fmaxnum>;