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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dflat-scratch-init.ll8 ; RW-FLAT: s_add_u32 flat_scratch_lo, s4, s7
9 ; RW-FLAT: s_addc_u32 flat_scratch_hi, s5, 0
10 ; RO-FLAT-NOT: flat_scratch
16 ; RW-FLAT-NOT: .amdhsa_enable_private_segment
21 ; RW-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 6
22 ; RO-FLAT: COMPUTE_PGM_RSRC2:USER_SGPR: 0
32 ; RO-FLAT-NOT: flat_scratch
33 ; RW-FLAT: buffer_store_dword
34 ; RO-FLAT: scratch_store_dword
40 ; RW-FLAT-NOT: .amdhsa_enable_private_segment
[all …]
H A Dinst-select-load-atomic-global.mir44 ; GFX7-FLAT-NEXT: {{ $}}
91 ; GFX7-FLAT-NEXT: {{ $}}
138 ; GFX7-FLAT-NEXT: {{ $}}
195 ; GFX7-FLAT-NEXT: {{ $}}
242 ; GFX7-FLAT-NEXT: {{ $}}
289 ; GFX7-FLAT-NEXT: {{ $}}
336 ; GFX7-FLAT-NEXT: {{ $}}
383 ; GFX7-FLAT-NEXT: {{ $}}
460 ; GFX7-FLAT-NEXT: {{ $}}
529 ; GFX7-FLAT-NEXT: {{ $}}
[all …]
H A Dinst-select-store-global.mir45 ; GFX7-FLAT-NEXT: {{ $}}
107 ; GFX7-FLAT-NEXT: {{ $}}
169 ; GFX7-FLAT-NEXT: {{ $}}
222 ; GFX7-FLAT-NEXT: {{ $}}
274 ; GFX7-FLAT-NEXT: {{ $}}
337 ; GFX7-FLAT-NEXT: {{ $}}
399 ; GFX7-FLAT-NEXT: {{ $}}
452 ; GFX7-FLAT-NEXT: {{ $}}
505 ; GFX7-FLAT-NEXT: {{ $}}
558 ; GFX7-FLAT-NEXT: {{ $}}
[all …]
H A Dinst-select-amdgpu-atomic-cmpxchg-global.mir50 ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
51 ; GFX7-FLAT-NEXT: {{ $}}
134 ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3
135 ; GFX7-FLAT-NEXT: {{ $}}
241 ; GFX7-FLAT-NEXT: {{ $}}
325 ; GFX7-FLAT-NEXT: {{ $}}
451 ; GFX7-FLAT-NEXT: {{ $}}
553 ; GFX7-FLAT-NEXT: {{ $}}
628 ; GFX7-FLAT-NEXT: {{ $}}
705 ; GFX7-FLAT-NEXT: {{ $}}
[all …]
H A Dinst-select-load-global.mir47 ; GFX7-FLAT-NEXT: {{ $}}
116 ; GFX7-FLAT-NEXT: {{ $}}
185 ; GFX7-FLAT-NEXT: {{ $}}
254 ; GFX7-FLAT-NEXT: {{ $}}
323 ; GFX7-FLAT-NEXT: {{ $}}
382 ; GFX7-FLAT-NEXT: {{ $}}
441 ; GFX7-FLAT-NEXT: {{ $}}
500 ; GFX7-FLAT-NEXT: {{ $}}
559 ; GFX7-FLAT-NEXT: {{ $}}
618 ; GFX7-FLAT-NEXT: {{ $}}
[all …]
H A Dinst-select-load-global.s96.mir31 ; GFX7-FLAT-LABEL: name: load_global_v3s32
32 ; GFX7-FLAT: liveins: $vgpr0_vgpr1
33 ; GFX7-FLAT-NEXT: {{ $}}
34 ; GFX7-FLAT-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
78 ; GFX7-FLAT-LABEL: name: load_global_s96
79 ; GFX7-FLAT: liveins: $vgpr0_vgpr1
80 ; GFX7-FLAT-NEXT: {{ $}}
83 ; GFX7-FLAT-NEXT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
125 ; GFX7-FLAT-LABEL: name: load_global_v6s16
126 ; GFX7-FLAT: liveins: $vgpr0_vgpr1
[all …]
H A Dinst-select-store-global.s96.mir33 ; GFX7-FLAT-LABEL: name: store_global_v3s32
34 ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
35 ; GFX7-FLAT-NEXT: {{ $}}
36 ; GFX7-FLAT-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
80 ; GFX7-FLAT-LABEL: name: store_global_s96
81 ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
82 ; GFX7-FLAT-NEXT: {{ $}}
83 ; GFX7-FLAT-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
127 ; GFX7-FLAT-LABEL: name: store_global_v6s16
128 ; GFX7-FLAT: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3_vgpr4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsi-annotate-cf.ll40 ; FLAT-NEXT: .LBB0_1: ; %ENDIF
46 ; FLAT-NEXT: ; %bb.2: ; %ENDLOOP
49 ; FLAT-NEXT: s_mov_b32 s2, -1
52 ; FLAT-NEXT: s_endpgm
94 ; FLAT: ; %bb.0: ; %entry
101 ; FLAT-NEXT: ; %bb.1: ; %else
107 ; FLAT-NEXT: .LBB1_2: ; %endif
109 ; FLAT-NEXT: .LBB1_3: ; %loop
115 ; FLAT-NEXT: ; %bb.4: ; %exit
116 ; FLAT-NEXT: s_endpgm
[all …]
H A Dbitreverse.ll33 ; FLAT-LABEL: s_brev_i16:
34 ; FLAT: ; %bb.0:
44 ; FLAT-NEXT: s_endpgm
83 ; FLAT: ; %bb.0:
97 ; FLAT-NEXT: s_endpgm
134 ; FLAT: ; %bb.0:
181 ; FLAT: ; %bb.0:
238 ; FLAT: ; %bb.0:
290 ; FLAT: ; %bb.0:
348 ; FLAT: ; %bb.0:
[all …]
H A Dsi-annotate-cf-kill.ll46 ; FLAT-LABEL: uniform_kill:
47 ; FLAT: ; %bb.0: ; %entry
55 ; FLAT-NEXT: ; %bb.1: ; %if1
57 ; FLAT-NEXT: ; %bb.2: ; %endif1
63 ; FLAT-NEXT: ; %bb.3: ; %endif1
68 ; FLAT-NEXT: ; %bb.4: ; %if2
69 ; FLAT-NEXT: s_mov_b32 s3, 0
77 ; FLAT-NEXT: .LBB0_5: ; %endif2
80 ; FLAT-NEXT: .LBB0_6:
83 ; FLAT-NEXT: s_endpgm
[all …]
H A Dflat-scratch-reg.ll37 ; GFX9-ARCH-FLAT: ; NumSgprs: 14
38 ; GFX10-ARCH-FLAT: ; NumSgprs: 8
57 ; GFX9-ARCH-FLAT: ; NumSgprs: 14
77 ; GFX9-ARCH-FLAT: ; NumSgprs: 14
78 ; GFX10-ARCH-FLAT: ; NumSgprs: 8
97 ; GFX9-ARCH-FLAT: ; NumSgprs: 14
120 ; GFX9-ARCH-FLAT: ; NumSgprs: 6
121 ; GFX10-ARCH-FLAT: ; NumSgprs: 0
140 ; GFX9-ARCH-FLAT: ; NumSgprs: 6
141 ; GFX10-ARCH-FLAT: ; NumSgprs: 0
[all …]
/llvm-project-15.0.7/llvm/utils/
H A DGenLibDeps.pl14 my $FLAT = 0;
23 if (/^-flat$/) { $FLAT = 1; next; }
24 if (/^-why/) { $WHY = 1; $FLAT = 1; next; }
40 if (!$FLAT) {
201 if ($FLAT) {
278 if ($FLAT) {
293 if (!$FLAT) { print DOT "$lib_ns -> $key [ weight=0 ];\n" };
298 if ($FLAT) {
312 if (!$FLAT) {
353 if (!$FLAT) {
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AMDGPU/
H A Daddress-space-ptr-sze-gep-index-assert.ll31 ; CHECK-NEXT: [[FLAT:%.*]] = addrspacecast i32 addrspace(3)* [[LDS:%.*]] to i32*
35 ; CHECK-NEXT: [[FLAT_1:%.*]] = getelementptr inbounds i32, i32* [[FLAT]], i64 [[ADD1]]
38 ; CHECK-NEXT: [[LOAD_FLAT_0:%.*]] = load i32, i32* [[FLAT]], align 4
72 ; CHECK-NEXT: [[FLAT:%.*]] = addrspacecast i32 addrspace(1)* [[GLOBAL:%.*]] to i32*
76 ; CHECK-NEXT: [[FLAT_1:%.*]] = getelementptr inbounds i32, i32* [[FLAT]], i64 [[ADD1]]
79 ; CHECK-NEXT: [[LOAD_FLAT_0:%.*]] = load i32, i32* [[FLAT]], align 4
114 ; CHECK-NEXT: [[FLAT:%.*]] = addrspacecast i32 addrspace(3)* [[LDS:%.*]] to i32*
118 ; CHECK-NEXT: [[FLAT_1:%.*]] = getelementptr inbounds i32, i32* [[FLAT]], i64 [[ADD1]]
121 ; CHECK-NEXT: [[LOAD_FLAT_0:%.*]] = load i32, i32* [[FLAT]], align 4
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrFormats.td44 field bit FLAT = 0;
120 // This field indicates that FLAT instruction accesses FLAT_GLBL segment.
121 // Must be 0 for non-FLAT instructions.
140 // This field indicates that FLAT instruction accesses FLAT_SCRATCH segment.
141 // Must be 0 for non-FLAT instructions.
179 let TSFlags{22} = FLAT;
H A DSIPostRABundler.cpp61 SIInstrFlags::FLAT | SIInstrFlags::MIMG;
H A DAMDGPUInsertDelayAlu.cpp46 SIInstrFlags::FLAT | SIInstrFlags::MIMG | in instructionWaitsForVALU()
H A DSIDefines.h59 FLAT = 1 << 22, enumerator
H A DSIInstrInfo.h516 return MI.getDesc().TSFlags & SIInstrFlags::FLAT; in isFLAT()
549 return get(Opcode).TSFlags & SIInstrFlags::FLAT; in isFLAT()
H A DSIMemoryLegalizer.cpp77 FLAT = GLOBAL | LDS | SCRATCH, enumerator
672 return SIAtomicAddrSpace::FLAT; in toSIAtomicAddrSpace()
/llvm-project-15.0.7/llvm/test/Instrumentation/MemorySanitizer/
H A Dclmul.ll66 ; ORIGIN: %[[FLAT:.*]] = bitcast <8 x i64> %[[SHUF1]] to i512
67 ; ORIGIN: %[[I:.*]] = icmp ne i512 %[[FLAT]], 0
/llvm-project-15.0.7/openmp/runtime/src/
H A Dz_Windows_NT-586_asm.asm38 FLAT GROUP _DATA, CONST, _BSS label
39 ASSUME CS: FLAT, DS: FLAT, SS: FLAT
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dflat_gfx10.txt78 # FLAT opcodes: dlc support for atomics
178 # FLAT GLOBAL opcodes: dlc support for atomics
272 # FLAT GLOBAL opcodes: fcmpswap
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCA/
H A DAMDGPUCustomBehaviour.cpp252 } else if (MCID.TSFlags & SIInstrFlags::FLAT) { in generateWaitCntInfo()
/llvm-project-15.0.7/mlir/test/Dialect/Vector/
H A Dvector-transpose-lowering.mlir3 …-opt %s -test-vector-transpose-lowering=flat=1 -split-input-file | FileCheck %s --check-prefix=FLAT
30 // FLAT-LABEL: func @transpose(
40 // FLAT: vector.shape_cast {{.*}} : vector<2x4xf32> to vector<8xf32>
41 …// FLAT: vector.flat_transpose %{{.*}} {columns = 2 : i32, rows = 4 : i32} : vector<8xf32> -…
42 // FLAT: vector.shape_cast {{.*}} : vector<8xf32> to vector<4x2xf32>
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX908.rst36 FLAT section in Instructions

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