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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-fcmp.mir139 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
151 ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
163 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
188 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
200 ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
212 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
240 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
255 ; GFX8-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
270 ; GFX9-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
301 ; GFX7-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
[all …]
H A Dlegalize-intrinsic-amdgcn-fdiv-fast.mir19 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
20 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
47 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ogt), [[FABS]](s32), [[C]]
48 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = nsz G_SELECT [[FCMP]](s1), [[C1]], [[C2]]
H A Dlegalize-intrinsic-round.mir27 ; GFX6-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
28 ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
44 ; GFX8-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oge), [[FABS]](s32), [[C1]]
45 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
62 ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
190 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
208 ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
237 ; GFX6-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
264 ; GFX8-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
291 ; GFX9-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s1), [[OR]], [[C]]
[all …]
H A Dregbankselect-fcmp.mir19 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY2]](s32), [[COPY3]]
38 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY2]](s32), [[COPY1]]
57 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(uge), [[COPY1]](s32), [[COPY2]]
H A Dinst-select-fcmp.mir19 ; WAVE64-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
20 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
26 ; WAVE32-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
27 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
439 ; WAVE64-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
440 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
447 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
468 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
475 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
888 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
[all …]
H A Dinst-select-fcmp.s16.mir21 ; WAVE64-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
22 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
30 ; WAVE32-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
31 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
474 ; WAVE64-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
475 ; WAVE64-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
483 ; WAVE32-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
484 ; WAVE32-NEXT: S_ENDPGM 0, implicit [[FCMP]](s1)
H A Dlegalize-frint.mir80 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
81 ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FADD1]]
196 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[FABS]](s64), [[C2]]
197 ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FADD1]]
H A Dirtranslator-constantexpr.ll72 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(oeq), [[UITOFP]](s32), [[C1]]
73 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[FCMP]](s1)
H A Dlegalize-ffloor.mir50 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[COPY]](s64), [[COPY]]
51 ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
120 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = nsz G_FCMP floatpred(ord), [[COPY]](s64), [[COPY]]
121 ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = nsz G_SELECT [[FCMP]](s1), [[COPY]], [[FMINNUM_IEEE]]
275 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ord), [[UV]](s64), [[UV]]
276 ; SI-NEXT: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[FCMP]](s1), [[UV]], [[FMINNUM_IEEE]]
H A Dlegalize-fceil.mir125 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY]](s64), [[C8]]
127 ; SI-NEXT: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
319 ; SI-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UV]](s64), [[C8]]
321 ; SI-NEXT: [[AND2:%[0-9]+]]:_(s1) = G_AND [[FCMP]], [[FCMP1]]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
H A Dfcmp.mir22 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
23 ; FP32: $v0 = COPY [[FCMP]](s32)
29 ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
30 ; FP64: $v0 = COPY [[FCMP]](s32)
52 ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
53 ; FP32: $v0 = COPY [[FCMP]](s32)
59 ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
60 ; FP64: $v0 = COPY [[FCMP]](s32)
H A Dfptosi_and_fptoui.mir347 ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
362 ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
391 ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
408 ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
440 ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
457 ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
529 ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
544 ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
573 ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
590 ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C2]]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dx86_64-legalize-fcmp.mir169 ; CHECK: $al = COPY [[FCMP]](s8)
203 ; CHECK: $al = COPY [[FCMP]](s8)
237 ; CHECK: $al = COPY [[FCMP]](s8)
271 ; CHECK: $al = COPY [[FCMP]](s8)
305 ; CHECK: $al = COPY [[FCMP]](s8)
339 ; CHECK: $al = COPY [[FCMP]](s8)
373 ; CHECK: $al = COPY [[FCMP]](s8)
407 ; CHECK: $al = COPY [[FCMP]](s8)
441 ; CHECK: $al = COPY [[FCMP]](s8)
475 ; CHECK: $al = COPY [[FCMP]](s8)
[all …]
H A Dregbankselect-X86_64.mir2533 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2580 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2627 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2674 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2721 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2768 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2815 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2862 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2909 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
2956 ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[FCMP]](s8)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dfcmp.mir23 ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
24 ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
31 ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s32), [[COPY1]]
32 ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
56 ; FP32: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
57 ; FP32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
64 ; FP64: [[FCMP:%[0-9]+]]:gprb(s32) = G_FCMP floatpred(oeq), [[COPY]](s64), [[COPY1]]
65 ; FP64: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[FCMP]](s32)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dretry-artifact-combine.mir10 ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ogt), [[COPY]](s32), [[COPY1]]
12 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[FCMP]], [[C]]
H A Dlegalize-fcmp.mir12 ; CHECK: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(oge), [[COPY]](s64), [[COPY1]]
13 ; CHECK: $w0 = COPY [[FCMP]](s32)
H A Dregbank-fp-use-def.mir29 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[C]](s32), [[LOAD]]
30 ; CHECK-NEXT: $w0 = COPY [[FCMP]](s32)
53 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:gpr(s32) = G_FCMP floatpred(uno), [[UV]](s32), [[UV1]]
54 ; CHECK-NEXT: $w0 = COPY [[FCMP]](s32)
H A Dprelegalizercombiner-invert-cmp.mir43 ; CHECK: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ule), [[COPY]](s64), [[C]]
44 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FCMP]](s1)
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-fp-compares.ll9 ; FCMP OEQ
343 ; FCMP UEQ
367 ; FCMP ONE
391 ; FCMP UNE
413 ; FCMP OGT
643 ; FCMP EQ
665 ; FCMP NE
687 ; FCMP GT
709 ; FCMP LT
731 ; FCMP GE
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A D2008-11-08-FCmp.ll4 ; When inst combining an FCMP with the LHS coming from a uitofp instruction, we
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dscalable-reductions.ll267 ; CHECK: %[[FCMP:.*]] = fcmp olt <vscale x 8 x float> %[[SEL1]], %[[SEL2]]
268 ; CHECK-NEXT: %[[SEL:.*]] = select <vscale x 8 x i1> %[[FCMP]], <vscale x 8 x float> %[[SEL1]], <vs…
301 ; CHECK: %[[FCMP:.*]] = fcmp fast ogt <vscale x 8 x float> %[[SEL1]], %[[SEL2]]
302 ; CHECK-NEXT: %[[SEL:.*]] = select fast <vscale x 8 x i1> %[[FCMP]], <vscale x 8 x float> %[[SEL1]]…
H A Dscalable-reduction-inloop-cond.ll146 ; CHECK-NEXT: [[FCMP:%.*]] = fcmp fast olt float [[RDX]], [[TMP18]]
147 ; CHECK-NEXT: [[FSEL:%.*]] = select fast i1 [[FCMP]], float [[RDX]], float [[TMP18]]
H A Dscalable-strict-fadd.ll356 ; CHECK-ORDERED: %[[FCMP:.*]] = fcmp une <vscale x 4 x float> %[[LOAD]], zeroinitializer
357 …v4f32.p0nxv4f32(<vscale x 4 x float>* {{.*}}, i32 4, <vscale x 4 x i1> %[[FCMP]], <vscale x 4 x fl…
358 ; CHECK-ORDERED: %[[XOR:.*]] = xor <vscale x 4 x i1> %[[FCMP]], shufflevector (<vscale x 4 x i1> in…
379 ; CHECK-ORDERED-TF: %[[FCMP:.*]] = fcmp une <vscale x 4 x float> %[[LOAD]], zeroinitializer
380 …]] = select <vscale x 4 x i1> %[[ACTIVE_LANE_MASK]], <vscale x 4 x i1> %[[FCMP]], <vscale x 4 x i1…
382 ; CHECK-ORDERED-TF: %[[XOR:.*]] = xor <vscale x 4 x i1> %[[FCMP]], shufflevector (<vscale x 4 x i1>…
405 ; CHECK-UNORDERED: %[[FCMP:.*]] = fcmp une <vscale x 4 x float> %[[LOAD1]], zeroinitializer
406 …v4f32.p0nxv4f32(<vscale x 4 x float>* {{.*}}, i32 4, <vscale x 4 x i1> %[[FCMP]], <vscale x 4 x fl…
407 ; CHECK-UNORDERED: %[[XOR:.*]] = xor <vscale x 4 x i1> %[[FCMP]], shufflevector (<vscale x 4 x i1> …
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/RISCV/
H A Dscalable-reductions.ll270 ; CHECK: %[[FCMP:.*]] = fcmp olt <vscale x 8 x float> %[[SEL1]], %[[SEL2]]
271 ; CHECK-NEXT: %[[SEL:.*]] = select <vscale x 8 x i1> %[[FCMP]], <vscale x 8 x float> %[[SEL1]], <vs…
304 ; CHECK: %[[FCMP:.*]] = fcmp fast ogt <vscale x 8 x float> %[[SEL1]], %[[SEL2]]
305 ; CHECK-NEXT: %[[SEL:.*]] = select fast <vscale x 8 x i1> %[[FCMP]], <vscale x 8 x float> %[[SEL1]]…

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